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[AArch64][NFC] Use member variable RI instead getRegisterInfo in copyPhysReg (llvm#162826)
This patch uses the RI member variable directly in the member function AArch64InstrInfo::copyPhysReg, instead of redundant calls to the public API. (cherry-pick 6345222)
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 38 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -5043,17 +5043,15 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50435043
bool RenamableSrc) const {
50445044
if (AArch64::GPR32spRegClass.contains(DestReg) &&
50455045
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
5046-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5047-
50485046
if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
50495047
// If either operand is WSP, expand to ADD #0.
50505048
if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50515049
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50525050
// Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
5053-
MCRegister DestRegX = TRI->getMatchingSuperReg(
5054-
DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5055-
MCRegister SrcRegX = TRI->getMatchingSuperReg(
5056-
SrcReg, AArch64::sub_32, &AArch64::GPR64spRegClass);
5051+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5052+
&AArch64::GPR64spRegClass);
5053+
MCRegister SrcRegX = RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5054+
&AArch64::GPR64spRegClass);
50575055
// This instruction is reading and writing X registers. This may upset
50585056
// the register scavenger and machine verifier, so we need to indicate
50595057
// that we are reading an undefined value from SrcRegX, but a proper
@@ -5076,14 +5074,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50765074
} else if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50775075
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50785076
// Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
5079-
MCRegister DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32,
5080-
&AArch64::GPR64spRegClass);
5077+
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
5078+
&AArch64::GPR64spRegClass);
50815079
assert(DestRegX.isValid() && "Destination super-reg not valid");
50825080
MCRegister SrcRegX =
50835081
SrcReg == AArch64::WZR
50845082
? AArch64::XZR
5085-
: TRI->getMatchingSuperReg(SrcReg, AArch64::sub_32,
5086-
&AArch64::GPR64spRegClass);
5083+
: RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5084+
&AArch64::GPR64spRegClass);
50875085
assert(SrcRegX.isValid() && "Source super-reg not valid");
50885086
// This instruction is reading and writing X registers. This may upset
50895087
// the register scavenger and machine verifier, so we need to indicate
@@ -5313,11 +5311,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53135311
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53145312
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53155313
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5316-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5317-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::dsub,
5318-
&AArch64::FPR128RegClass);
5319-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::dsub,
5320-
&AArch64::FPR128RegClass);
5314+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
5315+
&AArch64::FPR128RegClass);
5316+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
5317+
&AArch64::FPR128RegClass);
53215318
// This instruction is reading and writing Q registers. This may upset
53225319
// the register scavenger and machine verifier, so we need to indicate
53235320
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5338,11 +5335,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53385335
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53395336
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53405337
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5341-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5342-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5343-
&AArch64::FPR128RegClass);
5344-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5345-
&AArch64::FPR128RegClass);
5338+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5339+
&AArch64::FPR128RegClass);
5340+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5341+
&AArch64::FPR128RegClass);
53465342
// This instruction is reading and writing Q registers. This may upset
53475343
// the register scavenger and machine verifier, so we need to indicate
53485344
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5353,11 +5349,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53535349
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
53545350
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
53555351
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5356-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5357-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::ssub,
5358-
&AArch64::FPR64RegClass);
5359-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::ssub,
5360-
&AArch64::FPR64RegClass);
5352+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
5353+
&AArch64::FPR64RegClass);
5354+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
5355+
&AArch64::FPR64RegClass);
53615356
// This instruction is reading and writing D registers. This may upset
53625357
// the register scavenger and machine verifier, so we need to indicate
53635358
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5377,11 +5372,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53775372
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
53785373
!Subtarget.hasZeroCycleRegMoveFPR64() &&
53795374
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
5380-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5381-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5382-
&AArch64::FPR128RegClass);
5383-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5384-
&AArch64::FPR128RegClass);
5375+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5376+
&AArch64::FPR128RegClass);
5377+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5378+
&AArch64::FPR128RegClass);
53855379
// This instruction is reading and writing Q registers. This may upset
53865380
// the register scavenger and machine verifier, so we need to indicate
53875381
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5392,11 +5386,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
53925386
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
53935387
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
53945388
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5395-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5396-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::hsub,
5397-
&AArch64::FPR64RegClass);
5398-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::hsub,
5399-
&AArch64::FPR64RegClass);
5389+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
5390+
&AArch64::FPR64RegClass);
5391+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
5392+
&AArch64::FPR64RegClass);
54005393
// This instruction is reading and writing D registers. This may upset
54015394
// the register scavenger and machine verifier, so we need to indicate
54025395
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5420,11 +5413,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54205413
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
54215414
!Subtarget.hasZeroCycleRegMoveFPR64() &&
54225415
!Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
5423-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5424-
MCRegister DestRegQ = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5425-
&AArch64::FPR128RegClass);
5426-
MCRegister SrcRegQ = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5427-
&AArch64::FPR128RegClass);
5416+
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5417+
&AArch64::FPR128RegClass);
5418+
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5419+
&AArch64::FPR128RegClass);
54285420
// This instruction is reading and writing Q registers. This may upset
54295421
// the register scavenger and machine verifier, so we need to indicate
54305422
// that we are reading an undefined value from SrcRegQ, but a proper
@@ -5435,11 +5427,10 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
54355427
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
54365428
} else if (Subtarget.hasZeroCycleRegMoveFPR64() &&
54375429
!Subtarget.hasZeroCycleRegMoveFPR32()) {
5438-
const TargetRegisterInfo *TRI = &getRegisterInfo();
5439-
MCRegister DestRegD = TRI->getMatchingSuperReg(DestReg, AArch64::bsub,
5440-
&AArch64::FPR64RegClass);
5441-
MCRegister SrcRegD = TRI->getMatchingSuperReg(SrcReg, AArch64::bsub,
5442-
&AArch64::FPR64RegClass);
5430+
MCRegister DestRegD = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
5431+
&AArch64::FPR64RegClass);
5432+
MCRegister SrcRegD = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
5433+
&AArch64::FPR64RegClass);
54435434
// This instruction is reading and writing D registers. This may upset
54445435
// the register scavenger and machine verifier, so we need to indicate
54455436
// that we are reading an undefined value from SrcRegD, but a proper
@@ -5511,9 +5502,8 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
55115502
}
55125503

55135504
#ifndef NDEBUG
5514-
const TargetRegisterInfo &TRI = getRegisterInfo();
5515-
errs() << TRI.getRegAsmName(DestReg) << " = COPY "
5516-
<< TRI.getRegAsmName(SrcReg) << "\n";
5505+
errs() << RI.getRegAsmName(DestReg) << " = COPY " << RI.getRegAsmName(SrcReg)
5506+
<< "\n";
55175507
#endif
55185508
llvm_unreachable("unimplemented reg-to-reg copy");
55195509
}

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