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[AArch64] Improve lowering of GPR zeroing in copyPhysReg (llvm#163059)
This patch pivots GPR32 and GPR64 zeroing into distinct branches to simplify the code an improve the lowering. Zeroing GPR moves are now handled differently than non-zeroing ones. Zero source registers WZR and XZR do not require register annotations of undef, implicit and kill. The non-zeroing source now cannot process WZR removing the ternary expression. This patch also moves GPR64 logic right after GPR32 for better organization. (cherry-pick 5ac616f)
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-108
lines changed

2 files changed

+97
-108
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 48 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -5042,7 +5042,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50425042
bool RenamableDest,
50435043
bool RenamableSrc) const {
50445044
if (AArch64::GPR32spRegClass.contains(DestReg) &&
5045-
(AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) {
5045+
AArch64::GPR32spRegClass.contains(SrcReg)) {
50465046
if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
50475047
// If either operand is WSP, expand to ADD #0.
50485048
if (Subtarget.hasZeroCycleRegMoveGPR64() &&
@@ -5067,21 +5067,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
50675067
.addImm(0)
50685068
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
50695069
}
5070-
} else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGPR32()) {
5071-
BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
5072-
.addImm(0)
5073-
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
50745070
} else if (Subtarget.hasZeroCycleRegMoveGPR64() &&
50755071
!Subtarget.hasZeroCycleRegMoveGPR32()) {
50765072
// Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
50775073
MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32,
50785074
&AArch64::GPR64spRegClass);
50795075
assert(DestRegX.isValid() && "Destination super-reg not valid");
5080-
MCRegister SrcRegX =
5081-
SrcReg == AArch64::WZR
5082-
? AArch64::XZR
5083-
: RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5084-
&AArch64::GPR64spRegClass);
5076+
MCRegister SrcRegX = RI.getMatchingSuperReg(SrcReg, AArch64::sub_32,
5077+
&AArch64::GPR64spRegClass);
50855078
assert(SrcRegX.isValid() && "Source super-reg not valid");
50865079
// This instruction is reading and writing X registers. This may upset
50875080
// the register scavenger and machine verifier, so we need to indicate
@@ -5100,6 +5093,51 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51005093
return;
51015094
}
51025095

5096+
// GPR32 zeroing
5097+
if (AArch64::GPR32spRegClass.contains(DestReg) && SrcReg == AArch64::WZR) {
5098+
if (Subtarget.hasZeroCycleZeroingGPR32()) {
5099+
BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
5100+
.addImm(0)
5101+
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
5102+
} else {
5103+
BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
5104+
.addReg(AArch64::WZR)
5105+
.addReg(AArch64::WZR);
5106+
}
5107+
return;
5108+
}
5109+
5110+
if (AArch64::GPR64spRegClass.contains(DestReg) &&
5111+
AArch64::GPR64spRegClass.contains(SrcReg)) {
5112+
if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
5113+
// If either operand is SP, expand to ADD #0.
5114+
BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
5115+
.addReg(SrcReg, getKillRegState(KillSrc))
5116+
.addImm(0)
5117+
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
5118+
} else {
5119+
// Otherwise, expand to ORR XZR.
5120+
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
5121+
.addReg(AArch64::XZR)
5122+
.addReg(SrcReg, getKillRegState(KillSrc));
5123+
}
5124+
return;
5125+
}
5126+
5127+
// GPR64 zeroing
5128+
if (AArch64::GPR64spRegClass.contains(DestReg) && SrcReg == AArch64::XZR) {
5129+
if (Subtarget.hasZeroCycleZeroingGPR64()) {
5130+
BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
5131+
.addImm(0)
5132+
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
5133+
} else {
5134+
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
5135+
.addReg(AArch64::XZR)
5136+
.addReg(AArch64::XZR);
5137+
}
5138+
return;
5139+
}
5140+
51035141
// Copy a Predicate register by ORRing with itself.
51045142
if (AArch64::PPRRegClass.contains(DestReg) &&
51055143
AArch64::PPRRegClass.contains(SrcReg)) {
@@ -5184,27 +5222,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
51845222
return;
51855223
}
51865224

5187-
if (AArch64::GPR64spRegClass.contains(DestReg) &&
5188-
(AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) {
5189-
if (DestReg == AArch64::SP || SrcReg == AArch64::SP) {
5190-
// If either operand is SP, expand to ADD #0.
5191-
BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
5192-
.addReg(SrcReg, getKillRegState(KillSrc))
5193-
.addImm(0)
5194-
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
5195-
} else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGPR64()) {
5196-
BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
5197-
.addImm(0)
5198-
.addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
5199-
} else {
5200-
// Otherwise, expand to ORR XZR.
5201-
BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
5202-
.addReg(AArch64::XZR)
5203-
.addReg(SrcReg, getKillRegState(KillSrc));
5204-
}
5205-
return;
5206-
}
5207-
52085225
// Copy a DDDD register quad by copying the individual sub-registers.
52095226
if (AArch64::DDDDRegClass.contains(DestReg) &&
52105227
AArch64::DDDDRegClass.contains(SrcReg)) {

‎llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir‎

Lines changed: 49 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,12 @@
1-
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,-zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \
3-
# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ %s
4-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,-zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \
5-
# RUN: | FileCheck --check-prefix=CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ %s
6-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,+zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \
7-
# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ %s
8-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,+zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \
9-
# RUN: | FileCheck --check-prefix=CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ %s
10-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,-zcm-gpr64,+zcz-gpr32,+zcz-gpr64" %s \
11-
# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-ZCZ %s
12-
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,+zcm-gpr64,+zcz-gpr32,+zcz-gpr64" %s \
13-
# RUN: | FileCheck --check-prefix=CHECK-ZCM-ZCZ %s
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
2+
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,-zcz-gpr64" %s \
3+
# RUN: | FileCheck --check-prefix=CHECK-NOZCZ-GPR32-NOZCZ-GPR64 %s
4+
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,-zcz-gpr64" %s \
5+
# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-NOZCZ-GPR64 %s
6+
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,+zcz-gpr64" %s \
7+
# RUN: | FileCheck --check-prefix=CHECK-NOZCZ-GPR32-ZCZ-GPR64 %s
8+
# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,+zcz-gpr64" %s \
9+
# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-ZCZ-GPR64 %s
1410

1511
--- |
1612
define void @f0(i64 noundef %x) { ret void }
@@ -24,41 +20,29 @@ liveins:
2420
body: |
2521
bb.0:
2622
liveins: $x0, $lr
27-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f0
28-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
29-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
30-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr
31-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
23+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f0
24+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr
25+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}}
26+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr
27+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
3228
;
33-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f0
34-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
35-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
36-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr
37-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
29+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f0
30+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr
31+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}}
32+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0
33+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
3834
;
39-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0
40-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
41-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
42-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, undef $xzr, implicit $wzr
43-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
35+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0
36+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr
37+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}}
38+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr
39+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
4440
;
45-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0
46-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
47-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
48-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr
49-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
50-
;
51-
; CHECK-NO-ZCM-ZCZ-LABEL: name: f0
52-
; CHECK-NO-ZCM-ZCZ: liveins: $x0, $lr
53-
; CHECK-NO-ZCM-ZCZ-NEXT: {{ $}}
54-
; CHECK-NO-ZCM-ZCZ-NEXT: $w0 = MOVZWi 0, 0
55-
; CHECK-NO-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
56-
;
57-
; CHECK-ZCM-ZCZ-LABEL: name: f0
58-
; CHECK-ZCM-ZCZ: liveins: $x0, $lr
59-
; CHECK-ZCM-ZCZ-NEXT: {{ $}}
60-
; CHECK-ZCM-ZCZ-NEXT: $w0 = MOVZWi 0, 0
61-
; CHECK-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
41+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0
42+
; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr
43+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}}
44+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0
45+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
6246
$w0 = COPY $wzr
6347
BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
6448
...
@@ -69,41 +53,29 @@ liveins:
6953
body: |
7054
bb.0:
7155
liveins: $x0, $lr
72-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f1
73-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
74-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
75-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr
76-
; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
77-
;
78-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f1
79-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
80-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
81-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr
82-
; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
83-
;
84-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f1
85-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
86-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
87-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr
88-
; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
56+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f1
57+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr
58+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}}
59+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr
60+
; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
8961
;
90-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f1
91-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr
92-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}}
93-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr
94-
; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
62+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f1
63+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr
64+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}}
65+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr
66+
; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
9567
;
96-
; CHECK-NO-ZCM-ZCZ-LABEL: name: f1
97-
; CHECK-NO-ZCM-ZCZ: liveins: $x0, $lr
98-
; CHECK-NO-ZCM-ZCZ-NEXT: {{ $}}
99-
; CHECK-NO-ZCM-ZCZ-NEXT: $x0 = MOVZXi 0, 0
100-
; CHECK-NO-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
68+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1
69+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr
70+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}}
71+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0
72+
; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
10173
;
102-
; CHECK-ZCM-ZCZ-LABEL: name: f1
103-
; CHECK-ZCM-ZCZ: liveins: $x0, $lr
104-
; CHECK-ZCM-ZCZ-NEXT: {{ $}}
105-
; CHECK-ZCM-ZCZ-NEXT: $x0 = MOVZXi 0, 0
106-
; CHECK-ZCM-ZCZ-NEXT:BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
74+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1
75+
; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr
76+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}}
77+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0
78+
; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
10779
$x0 = COPY $xzr
10880
BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
10981
...

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