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jmorseSterling-Augustine
jmorse
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[NFC] Reapply 3f37c51, SmallDenseMap speedups
This time with 100% more building unit tests. Original commit message follows. [NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (llvm#109417) If we use SmallDenseMaps instead of DenseMaps at these locations, we get a substantial speedup because there's less spurious malloc traffic. Discovered by instrumenting DenseMap with some accounting code, then selecting sites where we'll get the most bang for our buck.
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15 files changed

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-106
lines changed

15 files changed

+109
-106
lines changed

‎llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,7 @@ class MemoryDependenceResults {
492492
const MemoryLocation &Loc, bool isLoad,
493493
BasicBlock *BB,
494494
SmallVectorImpl<NonLocalDepResult> &Result,
495-
DenseMap<BasicBlock *, Value *> &Visited,
495+
SmallDenseMap<BasicBlock *, Value *, 16> &Visited,
496496
bool SkipFirstBlock = false,
497497
bool IsIncomplete = false);
498498
MemDepResult getNonLocalInfoForBlock(Instruction *QueryInst,

‎llvm/include/llvm/Analysis/SparsePropagation.h‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -87,10 +87,9 @@ template <class LatticeKey, class LatticeVal> class AbstractLatticeFunction {
8787
/// ComputeInstructionState - Compute the LatticeKeys that change as a result
8888
/// of executing instruction \p I. Their associated LatticeVals are store in
8989
/// \p ChangedValues.
90-
virtual void
91-
ComputeInstructionState(Instruction &I,
92-
DenseMap<LatticeKey, LatticeVal> &ChangedValues,
93-
SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
90+
virtual void ComputeInstructionState(
91+
Instruction &I, SmallDenseMap<LatticeKey, LatticeVal, 16> &ChangedValues,
92+
SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
9493

9594
/// PrintLatticeVal - Render the given LatticeVal to the specified stream.
9695
virtual void PrintLatticeVal(LatticeVal LV, raw_ostream &OS);
@@ -401,7 +400,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitPHINode(PHINode &PN) {
401400
// computed from its incoming values. For example, SSI form stores its sigma
402401
// functions as PHINodes with a single incoming value.
403402
if (LatticeFunc->IsSpecialCasedPHI(&PN)) {
404-
DenseMap<LatticeKey, LatticeVal> ChangedValues;
403+
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
405404
LatticeFunc->ComputeInstructionState(PN, ChangedValues, *this);
406405
for (auto &ChangedValue : ChangedValues)
407406
if (ChangedValue.second != LatticeFunc->getUntrackedVal())
@@ -456,7 +455,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitInst(Instruction &I) {
456455

457456
// Otherwise, ask the transfer function what the result is. If this is
458457
// something that we care about, remember it.
459-
DenseMap<LatticeKey, LatticeVal> ChangedValues;
458+
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
460459
LatticeFunc->ComputeInstructionState(I, ChangedValues, *this);
461460
for (auto &ChangedValue : ChangedValues)
462461
if (ChangedValue.second != LatticeFunc->getUntrackedVal())

‎llvm/lib/Analysis/MemoryDependenceAnalysis.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -888,7 +888,7 @@ void MemoryDependenceResults::getNonLocalPointerDependency(
888888
// each block. Because of critical edges, we currently bail out if querying
889889
// a block with multiple different pointers. This can happen during PHI
890890
// translation.
891-
DenseMap<BasicBlock *, Value *> Visited;
891+
SmallDenseMap<BasicBlock *, Value *, 16> Visited;
892892
if (getNonLocalPointerDepFromBB(QueryInst, Address, Loc, isLoad, FromBB,
893893
Result, Visited, true))
894894
return;
@@ -1038,7 +1038,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
10381038
Instruction *QueryInst, const PHITransAddr &Pointer,
10391039
const MemoryLocation &Loc, bool isLoad, BasicBlock *StartBB,
10401040
SmallVectorImpl<NonLocalDepResult> &Result,
1041-
DenseMap<BasicBlock *, Value *> &Visited, bool SkipFirstBlock,
1041+
SmallDenseMap<BasicBlock *, Value *, 16> &Visited, bool SkipFirstBlock,
10421042
bool IsIncomplete) {
10431043
// Look up the cached info for Pointer.
10441044
ValueIsLoadPair CacheKey(Pointer.getAddr(), isLoad);

‎llvm/lib/Analysis/ScalarEvolution.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2255,7 +2255,7 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op,
22552255
/// the common case where no interesting opportunities are present, and
22562256
/// is also used as a check to avoid infinite recursion.
22572257
static bool
2258-
CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M,
2258+
CollectAddOperandsWithScales(SmallDenseMap<const SCEV *, APInt, 16> &M,
22592259
SmallVectorImpl<const SCEV *> &NewOps,
22602260
APInt &AccumulatedConstant,
22612261
ArrayRef<const SCEV *> Ops, const APInt &Scale,
@@ -2753,7 +2753,7 @@ const SCEV *ScalarEvolution::getAddExpr(SmallVectorImpl<const SCEV *> &Ops,
27532753
// operands multiplied by constant values.
27542754
if (Idx < Ops.size() && isa<SCEVMulExpr>(Ops[Idx])) {
27552755
uint64_t BitWidth = getTypeSizeInBits(Ty);
2756-
DenseMap<const SCEV *, APInt> M;
2756+
SmallDenseMap<const SCEV *, APInt, 16> M;
27572757
SmallVector<const SCEV *, 8> NewOps;
27582758
APInt AccumulatedConstant(BitWidth, 0);
27592759
if (CollectAddOperandsWithScales(M, NewOps, AccumulatedConstant,

‎llvm/lib/CodeGen/CalcSpillWeights.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
222222

223223
bool IsExiting = false;
224224
std::set<CopyHint> CopyHints;
225-
DenseMap<unsigned, float> Hint;
225+
SmallDenseMap<unsigned, float, 8> Hint;
226226
for (MachineRegisterInfo::reg_instr_nodbg_iterator
227227
I = MRI.reg_instr_nodbg_begin(LI.reg()),
228228
E = MRI.reg_instr_nodbg_end();

‎llvm/lib/CodeGen/MachineLICM.cpp‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ namespace {
239239

240240
bool IsCheapInstruction(MachineInstr &MI) const;
241241

242-
bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
242+
bool CanCauseHighRegPressure(const SmallDenseMap<unsigned, int> &Cost,
243243
bool Cheap);
244244

245245
void UpdateBackTraceRegPressure(const MachineInstr *MI);
@@ -264,9 +264,9 @@ namespace {
264264

265265
void InitRegPressure(MachineBasicBlock *BB);
266266

267-
DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
268-
bool ConsiderSeen,
269-
bool ConsiderUnseenAsDef);
267+
SmallDenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
268+
bool ConsiderSeen,
269+
bool ConsiderUnseenAsDef);
270270

271271
void UpdateRegPressure(const MachineInstr *MI,
272272
bool ConsiderUnseenAsDef = false);
@@ -977,10 +977,10 @@ void MachineLICMImpl::UpdateRegPressure(const MachineInstr *MI,
977977
/// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
978978
/// figure out which usages are live-ins.
979979
/// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
980-
DenseMap<unsigned, int>
980+
SmallDenseMap<unsigned, int>
981981
MachineLICMImpl::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
982982
bool ConsiderUnseenAsDef) {
983-
DenseMap<unsigned, int> Cost;
983+
SmallDenseMap<unsigned, int> Cost;
984984
if (MI->isImplicitDef())
985985
return Cost;
986986
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
@@ -1248,7 +1248,7 @@ bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
12481248
/// Visit BBs from header to current BB, check if hoisting an instruction of the
12491249
/// given cost matrix can cause high register pressure.
12501250
bool MachineLICMImpl::CanCauseHighRegPressure(
1251-
const DenseMap<unsigned, int> &Cost, bool CheapInstr) {
1251+
const SmallDenseMap<unsigned, int> &Cost, bool CheapInstr) {
12521252
for (const auto &RPIdAndCost : Cost) {
12531253
if (RPIdAndCost.second <= 0)
12541254
continue;

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp‎

Lines changed: 21 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -82,8 +82,7 @@ static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
8282
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
8383
/// implicit physical register output.
8484
void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
85-
Register SrcReg,
86-
DenseMap<SDValue, Register> &VRBaseMap) {
85+
Register SrcReg, VRBaseMapType &VRBaseMap) {
8786
Register VRBase;
8887
if (SrcReg.isVirtual()) {
8988
// Just use the input register directly!
@@ -187,7 +186,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
187186
MachineInstrBuilder &MIB,
188187
const MCInstrDesc &II,
189188
bool IsClone, bool IsCloned,
190-
DenseMap<SDValue, Register> &VRBaseMap) {
189+
VRBaseMapType &VRBaseMap) {
191190
assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
192191
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
193192

@@ -265,8 +264,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
265264

266265
/// getVR - Return the virtual register corresponding to the specified result
267266
/// of the specified node.
268-
Register InstrEmitter::getVR(SDValue Op,
269-
DenseMap<SDValue, Register> &VRBaseMap) {
267+
Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
270268
if (Op.isMachineOpcode() &&
271269
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
272270
// Add an IMPLICIT_DEF instruction before every use.
@@ -280,7 +278,7 @@ Register InstrEmitter::getVR(SDValue Op,
280278
return VReg;
281279
}
282280

283-
DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
281+
VRBaseMapType::iterator I = VRBaseMap.find(Op);
284282
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
285283
return I->second;
286284
}
@@ -318,7 +316,7 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
318316
SDValue Op,
319317
unsigned IIOpNum,
320318
const MCInstrDesc *II,
321-
DenseMap<SDValue, Register> &VRBaseMap,
319+
VRBaseMapType &VRBaseMap,
322320
bool IsDebug, bool IsClone, bool IsCloned) {
323321
assert(Op.getValueType() != MVT::Other &&
324322
Op.getValueType() != MVT::Glue &&
@@ -395,12 +393,10 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
395393
/// AddOperand - Add the specified operand to the specified machine instr. II
396394
/// specifies the instruction information for the node, and IIOpNum is the
397395
/// operand number (in the II) that we are adding.
398-
void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
399-
SDValue Op,
400-
unsigned IIOpNum,
401-
const MCInstrDesc *II,
402-
DenseMap<SDValue, Register> &VRBaseMap,
403-
bool IsDebug, bool IsClone, bool IsCloned) {
396+
void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
397+
unsigned IIOpNum, const MCInstrDesc *II,
398+
VRBaseMapType &VRBaseMap, bool IsDebug,
399+
bool IsClone, bool IsCloned) {
404400
if (Op.isMachineOpcode()) {
405401
AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
406402
IsDebug, IsClone, IsCloned);
@@ -499,8 +495,7 @@ Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
499495

500496
/// EmitSubregNode - Generate machine code for subreg nodes.
501497
///
502-
void InstrEmitter::EmitSubregNode(SDNode *Node,
503-
DenseMap<SDValue, Register> &VRBaseMap,
498+
void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
504499
bool IsClone, bool IsCloned) {
505500
Register VRBase;
506501
unsigned Opc = Node->getMachineOpcode();
@@ -634,7 +629,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
634629
///
635630
void
636631
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
637-
DenseMap<SDValue, Register> &VRBaseMap) {
632+
VRBaseMapType &VRBaseMap) {
638633
Register VReg = getVR(Node->getOperand(0), VRBaseMap);
639634

640635
// Create the new VReg in the destination class and emit a copy.
@@ -653,9 +648,8 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
653648

654649
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
655650
///
656-
void InstrEmitter::EmitRegSequence(SDNode *Node,
657-
DenseMap<SDValue, Register> &VRBaseMap,
658-
bool IsClone, bool IsCloned) {
651+
void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
652+
bool IsClone, bool IsCloned) {
659653
unsigned DstRCIdx = Node->getConstantOperandVal(0);
660654
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
661655
Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
@@ -703,7 +697,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node,
703697
///
704698
MachineInstr *
705699
InstrEmitter::EmitDbgValue(SDDbgValue *SD,
706-
DenseMap<SDValue, Register> &VRBaseMap) {
700+
VRBaseMapType &VRBaseMap) {
707701
DebugLoc DL = SD->getDebugLoc();
708702
assert(cast<DILocalVariable>(SD->getVariable())
709703
->isValidLocationForIntrinsic(DL) &&
@@ -755,7 +749,7 @@ MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
755749
void InstrEmitter::AddDbgValueLocationOps(
756750
MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
757751
ArrayRef<SDDbgOperand> LocationOps,
758-
DenseMap<SDValue, Register> &VRBaseMap) {
752+
VRBaseMapType &VRBaseMap) {
759753
for (const SDDbgOperand &Op : LocationOps) {
760754
switch (Op.getKind()) {
761755
case SDDbgOperand::FRAMEIX:
@@ -786,7 +780,7 @@ void InstrEmitter::AddDbgValueLocationOps(
786780

787781
MachineInstr *
788782
InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
789-
DenseMap<SDValue, Register> &VRBaseMap) {
783+
VRBaseMapType &VRBaseMap) {
790784
MDNode *Var = SD->getVariable();
791785
const DIExpression *Expr = (DIExpression *)SD->getExpression();
792786
DebugLoc DL = SD->getDebugLoc();
@@ -862,7 +856,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
862856
// Look up the corresponding VReg for the given SDNode, if any.
863857
SDNode *Node = DbgOperand.getSDNode();
864858
SDValue Op = SDValue(Node, DbgOperand.getResNo());
865-
DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
859+
VRBaseMapType::iterator I = VRBaseMap.find(Op);
866860
// No VReg -> produce a DBG_VALUE $noreg instead.
867861
if (I == VRBaseMap.end())
868862
break;
@@ -928,7 +922,7 @@ MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
928922

929923
MachineInstr *
930924
InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
931-
DenseMap<SDValue, Register> &VRBaseMap) {
925+
VRBaseMapType &VRBaseMap) {
932926
MDNode *Var = SD->getVariable();
933927
DIExpression *Expr = SD->getExpression();
934928
DebugLoc DL = SD->getDebugLoc();
@@ -944,7 +938,7 @@ InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
944938

945939
MachineInstr *
946940
InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
947-
DenseMap<SDValue, Register> &VRBaseMap) {
941+
VRBaseMapType &VRBaseMap) {
948942
MDNode *Var = SD->getVariable();
949943
DIExpression *Expr = SD->getExpression();
950944
DebugLoc DL = SD->getDebugLoc();
@@ -996,7 +990,7 @@ InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
996990
///
997991
void InstrEmitter::
998992
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
999-
DenseMap<SDValue, Register> &VRBaseMap) {
993+
VRBaseMapType &VRBaseMap) {
1000994
unsigned Opc = Node->getMachineOpcode();
1001995

1002996
// Handle subreg insert/extract specially
@@ -1238,7 +1232,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
12381232
/// needed dependencies.
12391233
void InstrEmitter::
12401234
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1241-
DenseMap<SDValue, Register> &VRBaseMap) {
1235+
VRBaseMapType &VRBaseMap) {
12421236
switch (Node->getOpcode()) {
12431237
default:
12441238
#ifndef NDEBUG

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