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[RISCV][GISel] Stop promoting s32 G_ROTL/ROTR rotate amount to s64 on RV64.
There are no SelectionDAG patterns to share. GISel has its own patterns since it considers s32 a legal type and SDAG does not.
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4 files changed

+25
-31
lines changed

4 files changed

+25
-31
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp‎

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -204,13 +204,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
204204
getActionDefinitionsBuilder({G_FSHL, G_FSHR}).lower();
205205

206206
auto &RotateActions = getActionDefinitionsBuilder({G_ROTL, G_ROTR});
207-
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb()) {
208-
RotateActions.legalFor({{s32, sXLen}, {sXLen, sXLen}});
209-
// Widen s32 rotate amount to s64 so SDAG patterns will match.
210-
if (ST.is64Bit())
211-
RotateActions.widenScalarIf(all(typeIs(0, s32), typeIs(1, s32)),
212-
changeTo(1, sXLen));
213-
}
207+
if (ST.hasStdExtZbb() || ST.hasStdExtZbkb())
208+
RotateActions.legalFor({{s32, s32}, {sXLen, sXLen}});
214209
RotateActions.lower();
215210

216211
getActionDefinitionsBuilder(G_BITREVERSE).maxScalar(0, sXLen).lower();

‎llvm/lib/Target/RISCV/RISCVGISel.td‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -169,6 +169,7 @@ def : StPat<store, SD, GPR, PtrVT>;
169169
//===----------------------------------------------------------------------===//
170170

171171
def simm12i32 : ImmLeaf<i32, [{return isInt<12>(Imm);}]>;
172+
def uimm5i32 : ImmLeaf<i32, [{return isUInt<5>(Imm);}]>;
172173

173174
def zext_is_sext : PatFrag<(ops node:$src), (zext node:$src), [{
174175
KnownBits Known = CurDAG->computeKnownBits(N->getOperand(0), 0);
@@ -337,12 +338,13 @@ def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
337338
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
338339
def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
339340

340-
def : PatGprGpr<shiftopw<rotl>, ROLW, i32, i64>;
341-
def : PatGprGpr<shiftopw<rotr>, RORW, i32, i64>;
342-
def : PatGprImm<rotr, RORIW, uimm5, i32>;
341+
def : PatGprGpr<rotl, ROLW, i32, i32>;
342+
def : PatGprGpr<rotr, RORW, i32, i32>;
343+
def : Pat<(i32 (rotl GPR:$rs1, uimm5i32:$imm)),
344+
(RORIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
343345

344-
def : Pat<(i32 (rotl GPR:$rs1, uimm5:$rs2)),
345-
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
346+
def : Pat<(i32 (rotl GPR:$rs1, uimm5i32:$rs2)),
347+
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5i32:$rs2))>;
346348
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
347349

348350
let Predicates = [HasStdExtZbkb, IsRV64] in {

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir‎

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,8 @@ body: |
2424
%0:gprb(s64) = COPY $x10
2525
%1:gprb(s32) = G_TRUNC %0(s64)
2626
%2:gprb(s64) = COPY $x11
27-
%7:gprb(s64) = G_CONSTANT i64 4294967295
28-
%6:gprb(s64) = G_AND %2, %7
29-
%4:gprb(s32) = G_ROTL %1, %6(s64)
27+
%6:gprb(s32) = G_TRUNC %2(s64)
28+
%4:gprb(s32) = G_ROTL %1, %6(s32)
3029
%5:gprb(s64) = G_ANYEXT %4(s32)
3130
$x10 = COPY %5(s64)
3231
PseudoRET implicit $x10
@@ -75,9 +74,8 @@ body: |
7574
%0:gprb(s64) = COPY $x10
7675
%1:gprb(s32) = G_TRUNC %0(s64)
7776
%2:gprb(s64) = COPY $x11
78-
%7:gprb(s64) = G_CONSTANT i64 4294967295
79-
%6:gprb(s64) = G_AND %2, %7
80-
%4:gprb(s32) = G_ROTR %1, %6(s64)
77+
%6:gprb(s32) = G_TRUNC %2(s64)
78+
%4:gprb(s32) = G_ROTR %1, %6(s32)
8179
%5:gprb(s64) = G_ANYEXT %4(s32)
8280
$x10 = COPY %5(s64)
8381
PseudoRET implicit $x10
@@ -119,13 +117,13 @@ body: |
119117
; CHECK: liveins: $x10
120118
; CHECK-NEXT: {{ $}}
121119
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
122-
; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 17
120+
; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 15
123121
; CHECK-NEXT: $x10 = COPY [[RORIW]]
124122
; CHECK-NEXT: PseudoRET implicit $x10
125123
%0:gprb(s64) = COPY $x10
126124
%1:gprb(s32) = G_TRUNC %0(s64)
127-
%2:gprb(s64) = G_CONSTANT i64 15
128-
%3:gprb(s32) = G_ROTL %1, %2(s64)
125+
%2:gprb(s32) = G_CONSTANT i32 15
126+
%3:gprb(s32) = G_ROTL %1, %2(s32)
129127
%4:gprb(s64) = G_ANYEXT %3(s32)
130128
$x10 = COPY %4(s64)
131129
PseudoRET implicit $x10
@@ -167,13 +165,14 @@ body: |
167165
; CHECK: liveins: $x10
168166
; CHECK-NEXT: {{ $}}
169167
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
170-
; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 15
171-
; CHECK-NEXT: $x10 = COPY [[RORIW]]
168+
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 15
169+
; CHECK-NEXT: [[RORW:%[0-9]+]]:gpr = RORW [[COPY]], [[ADDI]]
170+
; CHECK-NEXT: $x10 = COPY [[RORW]]
172171
; CHECK-NEXT: PseudoRET implicit $x10
173172
%0:gprb(s64) = COPY $x10
174173
%1:gprb(s32) = G_TRUNC %0(s64)
175-
%2:gprb(s64) = G_CONSTANT i64 15
176-
%3:gprb(s32) = G_ROTR %1, %2(s64)
174+
%2:gprb(s32) = G_CONSTANT i32 15
175+
%3:gprb(s32) = G_ROTR %1, %2(s32)
177176
%4:gprb(s64) = G_ANYEXT %3(s32)
178177
$x10 = COPY %4(s64)
179178
PseudoRET implicit $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-rotate-rv64.mir‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -113,9 +113,8 @@ body: |
113113
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
114114
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
115115
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
116-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
117-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
118-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[AND]](s64)
116+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
117+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTL:%[0-9]+]]:_(s32) = G_ROTL [[TRUNC]], [[TRUNC1]](s32)
119118
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTL]](s32)
120119
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
121120
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10
@@ -273,9 +272,8 @@ body: |
273272
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
274273
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
275274
; RV64ZBB_OR_RV64ZBKB-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
276-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
277-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
278-
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[AND]](s64)
275+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
276+
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ROTR:%[0-9]+]]:_(s32) = G_ROTR [[TRUNC]], [[TRUNC1]](s32)
279277
; RV64ZBB_OR_RV64ZBKB-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ROTR]](s32)
280278
; RV64ZBB_OR_RV64ZBKB-NEXT: $x10 = COPY [[ANYEXT]](s64)
281279
; RV64ZBB_OR_RV64ZBKB-NEXT: PseudoRET implicit $x10

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