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StoventStovent
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Remove pc from Instruction struct
1 parent a12f1e4 commit 34cd48d

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6 files changed

+38
-40
lines changed

6 files changed

+38
-40
lines changed

‎m68000/src/disassembler.rs‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ use crate::status_register::disassemble_conditional_test;
1010
use crate::utils::bits;
1111

1212
pub fn disassemble_unknown_instruction(inst: &Instruction) -> String {
13-
format!("Unknown instruction {:04X} at {:#X}", inst.opcode, inst.pc)
13+
format!("Unknown instruction {:04X}", inst.opcode)
1414
}
1515

1616
pub fn disassemble_abcd(inst: &Instruction) -> String {
@@ -97,7 +97,7 @@ pub fn disassemble_asr(inst: &Instruction) -> String {
9797

9898
pub fn disassemble_bcc(inst: &Instruction) -> String {
9999
let (cc, disp) = inst.operands.condition_displacement();
100-
format!("B{} {disp} <{:#X}>", disassemble_conditional_test(cc), inst.pc.wrapping_add(2).wrapping_add(disp as u32))
100+
format!("B{} {disp}", disassemble_conditional_test(cc))
101101
}
102102

103103
pub fn disassemble_bchg(inst: &Instruction) -> String {
@@ -120,7 +120,7 @@ pub fn disassemble_bclr(inst: &Instruction) -> String {
120120

121121
pub fn disassemble_bra(inst: &Instruction) -> String {
122122
let disp = inst.operands.displacement();
123-
format!("BRA {disp} <{:#X}>", inst.pc.wrapping_add(2).wrapping_add(disp as u32))
123+
format!("BRA {disp}")
124124
}
125125

126126
pub fn disassemble_bset(inst: &Instruction) -> String {
@@ -134,7 +134,7 @@ pub fn disassemble_bset(inst: &Instruction) -> String {
134134

135135
pub fn disassemble_bsr(inst: &Instruction) -> String {
136136
let disp = inst.operands.displacement();
137-
format!("BSR {disp} <{:#X}>", inst.pc.wrapping_add(2).wrapping_add(disp as u32))
137+
format!("BSR {disp}")
138138
}
139139

140140
pub fn disassemble_btst(inst: &Instruction) -> String {
@@ -178,7 +178,7 @@ pub fn disassemble_cmpm(inst: &Instruction) -> String {
178178

179179
pub fn disassemble_dbcc(inst: &Instruction) -> String {
180180
let (cc, r, disp) = inst.operands.condition_register_displacement();
181-
format!("DB{} D{r}, {disp} <{:#X}>", disassemble_conditional_test(cc), inst.pc.wrapping_add(2).wrapping_add(disp as u32))
181+
format!("DB{} D{r}, {disp}", disassemble_conditional_test(cc))
182182
}
183183

184184
pub fn disassemble_divs(inst: &Instruction) -> String {
@@ -531,10 +531,11 @@ pub fn disassemble_unlk(inst: &Instruction) -> String {
531531
///
532532
/// let mut data: Vec<u8> = Vec::new();
533533
/// data.resize(4, 0); // Load the binary in data.
534-
/// let mut iter = data.iter_u16(0).unwrap();
534+
/// let pc = 0;
535+
/// let mut iter = data.iter_u16(pc).unwrap();
535536
/// let inst = Instruction::from_memory(&mut iter).unwrap();
536537
/// let disassemble = DLUT[DECODER[inst.opcode as usize] as usize];
537-
/// println!("{:#X} {}", inst.pc, disassemble(&inst));
538+
/// println!("{pc:#X} {}", disassemble(&inst));
538539
/// ```
539540
pub const DLUT: [fn(&Instruction) -> String; Isa::_Size as usize] = [
540541
disassemble_unknown_instruction,

‎m68000/src/instruction.rs‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,6 @@ use crate::utils::{bit, bits};
2121
pub struct Instruction {
2222
/// The opcode itself.
2323
pub opcode: u16,
24-
/// The address of the instruction.
25-
pub pc: u32,
2624
/// The operands.
2725
pub operands: Operands,
2826
}
@@ -31,14 +29,13 @@ impl Instruction {
3129
/// Decodes the given opcode.
3230
///
3331
/// Returns the decoded instruction.
34-
pub fn from_opcode<M: MemoryIterator + ?Sized>(opcode: u16, pc: u32, memory: &mut M) -> Self {
32+
pub fn from_opcode<M: MemoryIterator + ?Sized>(opcode: u16, memory: &mut M) -> Self {
3533
let isa = Isa::from(opcode);
3634
let decode = IsaEntry::<M>::ISA_ENTRY[isa as usize].decode;
3735
let operands = decode(opcode, memory);
3836

3937
Instruction {
4038
opcode,
41-
pc,
4239
operands,
4340
}
4441
}
@@ -48,9 +45,8 @@ impl Instruction {
4845
/// Returns the decoded instruction.
4946
/// Returns Err when there was an error when reading memory (Access or Address error).
5047
pub fn from_memory<M: MemoryIterator + ?Sized>(memory: &mut M) -> Result<Self, u8> {
51-
let pc = memory.next_address();
5248
let opcode = memory.next().ok_or(ACCESS_ERROR)?;
53-
Ok(Self::from_opcode(opcode, pc, memory))
49+
Ok(Self::from_opcode(opcode, memory))
5450
}
5551

5652
/// Disassemble the intruction.
@@ -150,7 +146,7 @@ impl Size {
150146
/// - 0 => Word
151147
/// - 1 => Long
152148
#[inline(always)]
153-
pub fn from_bit(d: bool) -> Self {
149+
pub const fn from_bit(d: bool) -> Self {
154150
match d {
155151
false => Self::Word,
156152
true => Self::Long,

‎m68000/src/interpreter.rs‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -537,9 +537,9 @@ impl<CPU: CpuDetails> M68000<CPU> {
537537
})
538538
}
539539

540-
pub(super) fn execute_bcc(&mut self, pc: u32, condition: u8, displacement: i16) -> InterpreterResult {
540+
pub(super) fn execute_bcc(&mut self, condition: u8, displacement: i16) -> InterpreterResult {
541541
if self.regs.sr.condition(condition) {
542-
self.regs.pc.0 = pc.wrapping_add(displacement as u32);
542+
self.regs.pc = self.current_pc + Wrapping(2) + Wrapping(displacement as u32);
543543
Ok(CPU::BCC_BRANCH)
544544
} else {
545545
Ok(if self.current_opcode as u8 == 0 {
@@ -604,8 +604,8 @@ impl<CPU: CpuDetails> M68000<CPU> {
604604
Ok(exec_time)
605605
}
606606

607-
pub(super) fn execute_bra(&mut self, pc: u32, disp: i16) -> InterpreterResult {
608-
self.regs.pc.0 = pc.wrapping_add(disp as u32);
607+
pub(super) fn execute_bra(&mut self, disp: i16) -> InterpreterResult {
608+
self.regs.pc = self.current_pc + Wrapping(2) + Wrapping(disp as u32);
609609

610610
Ok(if self.current_opcode as u8 == 0 {
611611
CPU::BRA_WORD
@@ -641,9 +641,9 @@ impl<CPU: CpuDetails> M68000<CPU> {
641641
Ok(exec_time)
642642
}
643643

644-
pub(super) fn execute_bsr<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, pc: u32, disp: i16) -> InterpreterResult {
644+
pub(super) fn execute_bsr<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, disp: i16) -> InterpreterResult {
645645
self.push_long(memory, self.regs.pc.0)?;
646-
self.regs.pc.0 = pc.wrapping_add(disp as u32);
646+
self.regs.pc = self.current_pc + Wrapping(2) + Wrapping(disp as u32);
647647

648648
Ok(if self.current_opcode as u8 == 0 {
649649
CPU::BSR_WORD
@@ -821,13 +821,13 @@ impl<CPU: CpuDetails> M68000<CPU> {
821821
}
822822
}
823823

824-
pub(super) fn execute_dbcc(&mut self, pc: u32, cc: u8, reg: u8, disp: i16) -> InterpreterResult {
824+
pub(super) fn execute_dbcc(&mut self, cc: u8, reg: u8, disp: i16) -> InterpreterResult {
825825
if !self.regs.sr.condition(cc) {
826826
let counter = (self.regs.d[reg as usize].0 as i16).wrapping_sub(1);
827827
self.regs.d_word(reg, counter as u16);
828828

829829
if counter != -1 {
830-
self.regs.pc.0 = pc.wrapping_add(disp as u32);
830+
self.regs.pc = self.current_pc + Wrapping(2) + Wrapping(disp as u32);
831831
Ok(CPU::DBCC_FALSE_BRANCH)
832832
} else {
833833
Ok(CPU::DBCC_FALSE_NO_BRANCH)
@@ -1318,11 +1318,11 @@ impl<CPU: CpuDetails> M68000<CPU> {
13181318
self.regs.a_mut(eareg).0 = addr;
13191319
} else {
13201320
let mut addr = if ea.mode.is_ariwpo() {
1321-
self.regs.a(eareg)
1322-
} else {
1323-
self.get_effective_address(&mut ea, &mut exec_time)
1324-
}
1325-
.even()?;
1321+
self.regs.a(eareg)
1322+
} else {
1323+
self.get_effective_address(&mut ea, &mut exec_time)
1324+
}
1325+
.even()?;
13261326

13271327
for reg in 0..8 {
13281328
if list & 1 != 0 {

‎m68000/src/interpreter_disassembler.rs‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
5252
cycle_count += self.process_pending_exceptions(memory);
5353
}
5454

55+
self.current_pc = self.regs.pc;
5556
let instruction = match self.get_next_instruction(memory) {
5657
Ok(i) => i,
5758
Err(e) => return (0, String::from(""), cycle_count, Some(e)),
@@ -74,7 +75,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
7475
Err(e) => Some(e),
7576
};
7677

77-
(instruction.pc, dis, cycle_count, exception)
78+
(self.current_pc.0, dis, cycle_count, exception)
7879
}
7980

8081
fn instruction_unknown_instruction<M: MemoryAccess + ?Sized>(&mut self, _: &mut M, _: &Instruction) -> InterpreterResult {
@@ -143,7 +144,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
143144

144145
fn instruction_bcc<M: MemoryAccess + ?Sized>(&mut self, _: &mut M, inst: &Instruction) -> InterpreterResult {
145146
let (condition, displacement) = inst.operands.condition_displacement();
146-
self.execute_bcc(inst.pc.wrapping_add(2), condition, displacement)
147+
self.execute_bcc(condition, displacement)
147148
}
148149

149150
fn instruction_bchg<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, inst: &Instruction) -> InterpreterResult {
@@ -158,7 +159,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
158159

159160
fn instruction_bra<M: MemoryAccess + ?Sized>(&mut self, _: &mut M, inst: &Instruction) -> InterpreterResult {
160161
let disp = inst.operands.displacement();
161-
self.execute_bra(inst.pc.wrapping_add(2), disp)
162+
self.execute_bra(disp)
162163
}
163164

164165
fn instruction_bset<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, inst: &Instruction) -> InterpreterResult {
@@ -168,7 +169,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
168169

169170
fn instruction_bsr<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, inst: &Instruction) -> InterpreterResult {
170171
let disp = inst.operands.displacement();
171-
self.execute_bsr(memory, inst.pc.wrapping_add(2), disp)
172+
self.execute_bsr(memory, disp)
172173
}
173174

174175
fn instruction_btst<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M, inst: &Instruction) -> InterpreterResult {
@@ -210,7 +211,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
210211

211212
fn instruction_dbcc<M: MemoryAccess + ?Sized>(&mut self, _: &mut M, inst: &Instruction) -> InterpreterResult {
212213
let (cc, reg, disp) = inst.operands.condition_register_displacement();
213-
self.execute_dbcc(inst.pc.wrapping_add(2), cc, reg, disp)
214+
self.execute_dbcc(cc, reg, disp)
214215
}
215216

216217
/// If a zero divide exception occurs, this method returns the effective address calculation time, and the

‎m68000/src/interpreter_fast.rs‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -102,6 +102,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
102102
cycle_count += self.process_pending_exceptions(memory);
103103
}
104104

105+
self.current_pc = self.regs.pc;
105106
let opcode = match self.get_next_word(memory) {
106107
Ok(op) => op,
107108
Err(e) => return (cycle_count, Some(e)),
@@ -206,11 +207,10 @@ impl<CPU: CpuDetails> M68000<CPU> {
206207
}
207208

208209
fn fast_bcc<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
209-
let pc = self.regs.pc.0;
210210
let opcode = self.current_opcode;
211211
let mut iter = self.iter_from_pc(memory)?;
212212
let (condition, displacement) = condition_displacement(opcode, &mut iter);
213-
self.execute_bcc(pc, condition, displacement)
213+
self.execute_bcc(condition, displacement)
214214
}
215215

216216
fn fast_bchg<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
@@ -228,11 +228,10 @@ impl<CPU: CpuDetails> M68000<CPU> {
228228
}
229229

230230
fn fast_bra<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
231-
let pc = self.regs.pc.0;
232231
let opcode = self.current_opcode;
233232
let mut iter = self.iter_from_pc(memory)?;
234233
let disp = displacement(opcode, &mut iter);
235-
self.execute_bra(pc, disp)
234+
self.execute_bra(disp)
236235
}
237236

238237
fn fast_bset<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
@@ -243,11 +242,10 @@ impl<CPU: CpuDetails> M68000<CPU> {
243242
}
244243

245244
fn fast_bsr<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
246-
let pc = self.regs.pc.0;
247245
let opcode = self.current_opcode;
248246
let mut iter = self.iter_from_pc(memory)?;
249247
let disp = displacement(opcode, &mut iter);
250-
self.execute_bsr(memory, pc, disp)
248+
self.execute_bsr(memory, disp)
251249
}
252250

253251
fn fast_btst<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
@@ -300,11 +298,10 @@ impl<CPU: CpuDetails> M68000<CPU> {
300298
}
301299

302300
fn fast_dbcc<M: MemoryAccess + ?Sized>(&mut self, memory: &mut M) -> InterpreterResult {
303-
let pc = self.regs.pc.0;
304301
let opcode = self.current_opcode;
305302
let mut iter = self.iter_from_pc(memory)?;
306303
let (cc, reg, disp) = condition_register_displacement(opcode, &mut iter);
307-
self.execute_dbcc(pc, cc, reg, disp)
304+
self.execute_dbcc(cc, reg, disp)
308305
}
309306

310307
/// If a zero divide exception occurs, this method returns the effective address calculation time, and the

‎m68000/src/lib.rs‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,8 @@ pub struct M68000<CPU: CpuDetails> {
201201
/// The registers of the CPU.
202202
pub regs: Registers,
203203

204+
/// The address of the current instruction being executed.
205+
current_pc: Wrapping<u32>,
204206
/// The opcode of the instruction currently executing.
205207
///
206208
/// Stored because it is an information of the long exception stack frame.
@@ -235,6 +237,7 @@ impl<CPU: CpuDetails> M68000<CPU> {
235237
Self {
236238
regs: Registers::default(),
237239

240+
current_pc: Wrapping(u32::MAX),
238241
current_opcode: 0xFFFF,
239242
stop: false,
240243
exceptions: BTreeSet::new(),

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