fixed typo

llpeterson · llpeterson · commit 86343e35b908 · 2021-11-04T14:59:12.000-07:00
diff --git a/future.rst b/future.rst
@@ -86,7 +86,7 @@ reason about correctness-by-construction.
 
 .. sidebar:: Top-Down Verification
 	     
-   *The approach to verifying networks described in this section is
+   *The approach to verifying networks described in this chapter is
    similar to the one used in chip design. At the top is a behavioral
    model; then at the register-transfer level is a Verilog or VHDL
    model; and eventually at the bottom are transistors, polygons and
