Skip to content

Commit 03bba52

Browse files
authored
Create testbench.sv
1 parent f9243e1 commit 03bba52

File tree

1 file changed

+57
-0
lines changed
  • LAB VI: DESIGN OF MAGNITUDE COMPARATOR, DECODER AND MULTIPLEXER CIRCUIT USING HDL/Q3

1 file changed

+57
-0
lines changed
Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
module testbench_3X8DECODER;
2+
reg t_x, t_y, t_z;
3+
wire t_d0, t_d1, t_d2, t_d3, t_d4, t_d5, t_d6, t_d7, t_s, t_c;
4+
circuit3 dut(t_x, t_y, t_z, t_d0, t_d1, t_d2, t_d3, t_d4, t_d5, t_d6, t_d7,
5+
t_s, t_c);
6+
7+
initial
8+
begin
9+
$dumpfile("dump.vcd");
10+
$dumpvars(0, dut);
11+
12+
#1
13+
t_x <= 0;
14+
t_y <= 0;
15+
t_z <= 0;
16+
17+
#1
18+
t_x <= 0;
19+
t_y <= 0;
20+
t_z <= 1;
21+
22+
#1
23+
t_x <= 0;
24+
t_y <= 1;
25+
t_z <= 0;
26+
27+
#1
28+
t_x <= 0;
29+
t_y <= 1;
30+
t_z <= 1;
31+
32+
#1
33+
t_x <= 1;
34+
t_y <= 0;
35+
t_z <= 0;
36+
37+
#1
38+
t_x <= 1;
39+
t_y <= 0;
40+
t_z <= 1;
41+
42+
#1
43+
t_x <= 1;
44+
t_y <= 1;
45+
t_z <= 0;
46+
47+
#1
48+
t_x <= 1;
49+
t_y <= 1;
50+
t_z <= 1;
51+
52+
#1
53+
54+
$finish();
55+
end
56+
endmodule
57+

0 commit comments

Comments
 (0)