Create q.v

Tan12d · web-flow · commit 2d98caaeac38 · 2023-07-15T01:39:06.000+05:30
diff --git a/LAB VII: CONSTRUCT, TEST AND INVESTIGATE THE OPERATION OF VARIOUS FLIP-FLOP CIRCUITS USING HDL/Q2/q.v b/LAB VII: CONSTRUCT, TEST AND INVESTIGATE THE OPERATION OF VARIOUS FLIP-FLOP CIRCUITS USING HDL/Q2/q.v
@@ -0,0 +1,12 @@
+// Q2. Design and test SR flip-flop.
+
+
+
+// design.sv
+
+// Data-Flow
+module circuit2(S, R, Q, T);
+  input     S, R;
+  output    Q, T;
+  assign    T = S || (Q && (!(R)));
+endmodule
