Update c.v

Author: Tan12d

LAB I: Examine the Operation of Logic Gates Using HDL/Q2/c)/c.v

@@ -7,7 +7,7 @@
 module Or(A, B, X)
   input  (A, B);
   output X;
-  wires  w1,w2;
+  wire   w1,w2;
   nand   G1(w1, A, A);
   nand   G2(w2, B, B);
   nand   G3(X, w1, w2);
@@ -17,7 +17,7 @@ endmodule
   module Or(A, B, X)
   input     (A, B);
   output    X;
-  wires     w1,w2;
+  wire      w1,w2;
     assign  w1 = !(A && A);
     assign  w2 = !(A && B);
     assign  X  = !(w1 && w2);