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Added Example : Multicore Scheduler
Signed-off-by: Aravind-Padma-Kumar <a-kumar13@ti.com>
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‎examples/makefile‎

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@@ -3,7 +3,7 @@ include ../imports.mak
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SUBDIRS := \
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custom_frequency_generator empty empty_c \
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fft/split_radix_fft_4k_single_core fft/split_radix_fft_post_processing \
6-
LCD_interface logic_scope pru_emif rpmsg_echo_linux spi_loopback
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LCD_interface logic_scope pru_emif spi_loopback multicore_scheduler
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# "make" or "make all" builds projects that match $(DEVICE) set in imports.mak
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all: ARGUMENTS = all

‎examples/multicore_scheduler/README.md‎

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# Multicore Scheduler
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This project uses IEP timer along with Task Manager in 6 cores to schedule tasks in 6 cores back to back with no delay in between. The tasks collectively generate a toggling pattern using PWM init state on a PIN (PWM2_A(BP.31)) and the toggling happens back to back with no delay in between. The project demonstrates how sequential tasks on multiple cores can be scheduled back-to-back without any scheduling delays if a time based scheduling strategy is used.
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## Overview
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Each of the 6 PRUs in ICSSG0 is loaded with a task and mapped to different compare vents as shown below:
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<figure>
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<img src="pictures/multicore_scheduling_overview.png" alt="Multicore Scheduler Overview" width = "500">
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<figcaption>Fig.1 : Multicore Scheduler Overview </figcaption>
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</figure>
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IEP timer Cmp0 event is used for cyclic task scheduling. The compare events are all triggered such they are at adjacent cycles from each other. The tasks either set output PIN to high or low such that toggling pattern is achieved. Since RTU and TXPRU cores do not have access to GPOs via R30, we could either use EDIO or toggling of PWM init state. THe current project uses PWM init state on AM243x. A timing diagram that shows how the sequential task execution achieves the desired toggling pattern for 333Mhz (3ns TIme period)is shown below:
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![multicore_scheduling_timing_diagram](pictures/multicore_scheduling_timing_diagram.png)
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## Configuration
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An overview into how the mapping is performed is discussed here. There are six projects, one for each core and PRU0 does all the event configuration and mapping in the file "pwm_toggle.asm" of project "PRU_Multicore_Scheduling_PRU0". It contains code or macros that can be used to change the configurations or mapping if needed:
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1. Compare event timings for 250 Mhz or 4ns time period:
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```
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; increment value for configured clock
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MS_TIMER_INC .set 4 ; 250 Mhz, 4ns
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; set CMP0 time to desired time period in ns
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; (COUNT - increment value) is set as count starts from 0
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MS_CMP0_TIME .set (100-MS_TIMER_INC) ; cycle time
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MS_CMP1_TIME .set 2000 ; CMP1 time
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MS_CMP2_TIME .set (2*MS_TIMER_INC) ; CMP2 time
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MS_CMP3_TIME .set (3*MS_TIMER_INC) ; CMP3 time
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MS_CMP4_TIME .set (4*MS_TIMER_INC) ; CMP4 time
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MS_CMP5_TIME .set (5*MS_TIMER_INC) ; CMP5 time
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MS_CMP6_TIME .set (6*MS_TIMER_INC) ; CMP6 time
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MS_CMP7_TIME .set (1*MS_TIMER_INC) ; CMP7 time
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```
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2. Task triggers are mapped to compare events as shown below:
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```
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TRG_EVENT_PRU0 .set IEP0_CMP_7
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TRG_EVENT_PRU1 .set IEP0_CMP_2
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TRG_EVENT_RTU1 .set IEP0_CMP_3
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TRG_EVENT_RTU0 .set IEP0_CMP_4
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TRG_EVENT_TXPRU1 .set IEP0_CMP_5
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TRG_EVENT_TXPRU0 .set IEP0_CMP_6
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```
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Event numbers of compare events are fixed for AM243 and are defined above this mapping as follows :
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```
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;relevant event mappings
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IEP0_CMP_0 .set (16+0)
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IEP0_CMP_1 .set (16+1)
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IEP0_CMP_2 .set (16+2)
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IEP0_CMP_3 .set (16+3)
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IEP0_CMP_4 .set (16+4)
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IEP0_CMP_5 .set (16+5)
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IEP0_CMP_6 .set (16+6)
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IEP0_CMP_7 .set (16+7)
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```
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Various tasks have to be mapped to the respective task manager in each core. The tasks in all cores are mapped to TS2_0 slot of the task manager as part of the code in the project that corresponds to that core. For example, 'FN_PWM_INIT_TOGGLE_PRU1_TASK' is the task to be called in PRU1 when the mapped event is triggered, and is mapped to TS2_0 as shown below in "main.c" of the project "PRU_Multicore_Scheduling_PRU1" as shown below:
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```
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HW_WR_REG32((TM_REG_BASE_RTU1+TASKS_MGR_TS2_PC_S0), (unsigned int) FN_PWM_INIT_TOGGLE_RTU1_TASK);
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```
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## How to Run
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The multicore scheduler is run on ICSSG0 and the output can be traced from PIN BP.31 (PWM2_A). To view the results, a scope has to be connected to PIN BP.31 according to default configuration. Following are the steps for running on CCS:
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1. Import six projects that correspond to six ICSSG0 PRU cores from "examples/multicore_scheduler/am243x-lp"
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2. Power up AM243x Launchpad and connect to target
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3. Load six cores with corresponding projects as follows:
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1. Project "multicore_scheduler_am243x-lp_icss_g0_pru0_fw_ti-pru-cgt" to core ICSSG0 PRU0
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2. Project "multicore_scheduler_am243x-lp_icss_g0_pru1_fw_ti-pru-cgt" to core ICSSG0 PRU1
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3. Project "multicore_scheduler_am243x-lp_icss_g0_rtu_pru0_fw_ti-pru-cgt" to core ICSSG0 RTU_PRU0
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4. Project "multicore_scheduler_am243x-lp_icss_g0_rtu_pru1_fw_ti-pru-cgt" to core ICSSG0 RTU_PRU1
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5. Project "multicore_scheduler_am243x-lp_icss_g0_tx_pru0_fw_ti-pru-cgt" to core ICSSG0 TX_PRU0
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6. Project "multicore_scheduler_am243x-lp_icss_g0_tx_pru1_fw_ti-pru-cgt" to core ICSSG0 TX_PRU1
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4. Run all the six cores in any order
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5. Connect a logic scope to pin BP.31 to observe the toggling pattern generated. An example for the pattern generated for 333Mhz clock is shown below :
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![PWM_init_toggle](pictures/multicore_scheduling_toggling.png)
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‎examples/multicore_scheduler/firmware/am243x-lp/icss_g0_pru0_fw/ti-pru-cgt/am243_am64_pru_pinmux.h‎

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/* ============================================================================
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* Copyright (C) 2002-2023 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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file: AM243_AM64_PRU_pinmux.inc
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brief: Device specific pinmux defines for direct PRU configuration
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SDK driver on PRU would consume too much memory
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This is a trade off between readablility and code size.
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author: Thomas Leyrer
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(C) Copyright 2024, Texas Instruments, Inc
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*/
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#ifndef AM243_AM64_PRU_pinmux_h
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#define AM243_AM64_PRU_pinmux_h
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// LOCK UNLOCK defines
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#define PAD_PARTITION0_L0 (0x000f1008)
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#define PAD_PARTITION0_L1 (0x000f100C)
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#define PAD_PARTITION1_L0 (0x000f5008)
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#define PAD_PARTITION1_L1 (0x000f500C)
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#define PAD_KEY0 (0x68EF3490)
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#define PAD_KEY1 (0xD172BC5A)
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// Input/Output defines
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#define PRU_GPI (0x00040001)
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#define PRU_GPO (0x00010000)
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#define IEP_SYNC_OUT (0x00010002)
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#define IEP_LATCH_IN (0x00040002)
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// ICSS_G0 PRU0
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#define PRG0_PRU0_GPO0 (0x000F4160)
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#define PRG0_PRU0_GPO1 (0x000F4164)
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#define PRG0_PRU0_GPO2 (0x000F4168)
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#define PRG0_PRU0_GPO3 (0x000F416C)
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#define PRG0_PRU0_GPO4 (0x000F4170)
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#define PRG0_PRU0_GPO5 (0x000F4174)
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#define PRG0_PRU0_GPO6 (0x000F4178)
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#define PRG0_PRU0_GPO7 (0x000F417C)
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#define PRG0_PRU0_GPO8 (0x000F4180)
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#define PRG0_PRU0_GPO9 (0x000F4184)
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#define PRG0_PRU0_GPO10 (0x000F4188)
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#define PRG0_PRU0_GPO11 (0x000F418C)
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#define PRG0_PRU0_GPO12 (0x000F4190)
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#define PRG0_PRU0_GPO13 (0x000F4194)
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#define PRG0_PRU0_GPO14 (0x000F4198)
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#define PRG0_PRU0_GPO15 (0x000F419C)
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#define PRG0_PRU0_GPO16 (0x000F41A0)
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#define PRG0_PRU0_GPO17 (0x000F41A4)
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#define PRG0_PRU0_GPO18 (0x000F41A8)
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#define PRG0_PRU0_GPO19 (0x000F41AC)
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// ICSS_G0 PRU1
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#define PRG0_PRU1_GPO0 (0x000F41B0)
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#define PRG0_PRU1_GPO1 (0x000F41B4)
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#define PRG0_PRU1_GPO2 (0x000F41B8)
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#define PRG0_PRU1_GPO3 (0x000F41BC)
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#define PRG0_PRU1_GPO4 (0x000F41C0)
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#define PRG0_PRU1_GPO5 (0x000F41C4)
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#define PRG0_PRU1_GPO6 (0x000F41C8)
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#define PRG0_PRU1_GPO7 (0x000F41CC)
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#define PRG0_PRU1_GPO8 (0x000F41D0)
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#define PRG0_PRU1_GPO9 (0x000F41D4)
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#define PRG0_PRU1_GPO10 (0x000F41D8)
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#define PRG0_PRU1_GPO11 (0x000F41DC)
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#define PRG0_PRU1_GPO12 (0x000F41E0)
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#define PRG0_PRU1_GPO13 (0x000F41E4)
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#define PRG0_PRU1_GPO14 (0x000F41E8)
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#define PRG0_PRU1_GPO15 (0x000F41EC)
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#define PRG0_PRU1_GPO16 (0x000F41F0)
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#define PRG0_PRU1_GPO17 (0x000F41F4)
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#define PRG0_PRU1_GPO18 (0x000F41F8)
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#define PRG0_PRU1_GPO19 (0x000F41FC)
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// ICSS_G1 PRU0
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#define PRG1_PRU0_GPO0 (0x000F40B8)
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#define PRG1_PRU0_GPO1 (0x000F40BC)
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#define PRG1_PRU0_GPO2 (0x000F40C0)
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#define PRG1_PRU0_GPO3 (0x000F40C4)
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#define PRG1_PRU0_GPO4 (0x000F40C8)
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#define PRG1_PRU0_GPO5 (0x000F40CC)
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#define PRG1_PRU0_GPO6 (0x000F40D0)
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#define PRG1_PRU0_GPO7 (0x000F40D4)
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#define PRG1_PRU0_GPO8 (0x000F40D8)
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#define PRG1_PRU0_GPO9 (0x000F40DC)
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#define PRG1_PRU0_GP010 (0x000F40E0)
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#define PRG1_PRU0_GPO11 (0x000F40E4)
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#define PRG1_PRU0_GPO12 (0x000F40E8)
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#define PRG1_PRU0_GPO13 (0x000F40EC)
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#define PRG1_PRU0_GPO14 (0x000F40F0)
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#define PRG1_PRU0_GPO15 (0x000F40F4)
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#define PRG1_PRU0_GPO16 (0x000F40F8)
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#define PRG1_PRU0_GPO17 (0x000F40FC)
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#define PRG1_PRU0_GPO18 (0x000F4100)
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#define PRG1_PRU0_GPO19 (0x000F4104)
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// ICSS_G1 PRU1
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#define PRG1_PRU1_GPO0 (0x000F4108)
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#define PRG1_PRU1_GPO1 (0x000F410C)
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#define PRG1_PRU1_GPO2 (0x000F4110)
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#define PRG1_PRU1_GPO3 (0x000F4114)
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#define PRG1_PRU1_GPO4 (0x000F4118)
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#define PRG1_PRU1_GPO5 (0x000F411C)
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#define PRG1_PRU1_GPO6 (0x000F4120)
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#define PRG1_PRU1_GPO7 (0x000F4124)
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#define PRG1_PRU1_GPO8 (0x000F4128)
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#define PRG1_PRU1_GPO9 (0x000F412C)
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#define PRG1_PRU1_GPO10 (0x000F4130)
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#define PRG1_PRU1_GPO11 (0x000F4134)
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#define PRG1_PRU1_GPO12 (0x000F4138)
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#define PRG1_PRU1_GPO13 (0x000F413C)
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#define PRG1_PRU1_GPO14 (0x000F4140)
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#define PRG1_PRU1_GPO15 (0x000F4144)
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#define PRG1_PRU1_GPO16 (0x000F4148)
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#define PRG1_PRU1_GPO17 (0x000F414C)
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#define PRG1_PRU1_GPO18 (0x000F4150)
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#define PRG1_PRU1_GPO19 (0x000F4154)
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#endif

‎examples/multicore_scheduler/firmware/am243x-lp/icss_g0_pru0_fw/ti-pru-cgt/example.projectspec‎

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<?xml version="1.0" encoding="UTF-8"?>
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<projectSpec>
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<applicability>
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<when>
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<context
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deviceFamily="PRU"
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deviceId="AM243x_LAUNCHPAD"
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/>
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</when>
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</applicability>
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<project
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title="Multicore Scheduler"
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name = "multicore_scheduler_am243x-lp_icss_g0_pru0_fw_ti-pru-cgt"
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products="com.ti.OPEN_PRU;com.ti.MCU_PLUS_SDK_AM243X"
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configurations="
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Debug,
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Release,
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"
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connection="TIXDS110_Connection.xml"
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toolChain="TI"
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cgtVersion="2.3.3"
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device="AM243x_LAUNCHPAD"
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deviceCore="ICSS_G0_PRU_0"
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ignoreDefaultDeviceSettings="true"
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ignoreDefaultCCSSettings="true"
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endianness="little"
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outputFormat="ELF"
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outputType="executable"
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compilerBuildOptions="
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-I${CG_TOOL_ROOT}/include
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-I${MCU_PLUS_SDK_PATH}/source
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-I${OPEN_PRU_PATH}/source
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-I${MCU_PLUS_SDK_PATH}/source/pru_io/firmware/common
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-DPRU0
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-DSLICE0
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-v4
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-DSOC_AM243X
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"
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linkerBuildOptions="
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-m=multicore_scheduler.${ConfigName}.map
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--disable_auto_rts
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--diag_suppress=10063-D
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-i${CG_TOOL_ROOT}/lib
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-i${CG_TOOL_ROOT}/include
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-llibc.a
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"
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postBuildStep="
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$(CG_TOOL_ROOT)/bin/hexpru --diag_wrap=off --array --array:name_prefix=PRU0Firmware -o pru0_load_bin.h multicore_scheduler_am243x-lp_icss_g0_pru0_fw_ti-pru-cgt.out;if ${CCS_HOST_OS} == linux cat ${MCU_PLUS_SDK_PATH}/source/pru_io/firmware/pru_load_bin_copyright.h pru0_load_bin.h > ${OPEN_PRU_PATH}/examples/multicore_scheduler/firmware/am243x-lp/pru0_load_bin.h ;if ${CCS_HOST_OS} == linux rm pru0_load_bin.h;if ${CCS_HOST_OS} == win32 $(CCS_INSTALL_DIR)/utils/cygwin/cat ${MCU_PLUS_SDK_PATH}/source/pru_io/firmware/pru_load_bin_copyright.h pru0_load_bin.h > ${OPEN_PRU_PATH}/examples/multicore_scheduler/firmware/am243x-lp/pru0_load_bin.h ;if ${CCS_HOST_OS} == win32 $(CCS_INSTALL_DIR)/utils/cygwin/rm pru0_load_bin.h;
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"
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description="A Multicore Scheduler FW project">
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<configuration name="Debug"
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compilerBuildOptions="
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-D_DEBUG_=1
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"
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linkerBuildOptions="
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"
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></configuration>
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<configuration name="Release"
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compilerBuildOptions="
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-O3
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"
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linkerBuildOptions="
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"
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></configuration>
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<pathVariable name="MCU_PLUS_SDK_PATH" path="${COM_TI_MCU_PLUS_SDK_AM243X_INSTALL_DIR}" scope="project" />
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<pathVariable name="OPEN_PRU_PATH" path="${COM_TI_OPEN_PRU_INSTALL_DIR}" scope="project" />
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<file path="./linker.cmd" openOnCreation="false" excludeFromBuild="false" action="copy">
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</file>
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<file path="./main.c" openOnCreation="false" excludeFromBuild="false" action="copy">
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</file>
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<file path="./pwm_toggle.asm" openOnCreation="false" excludeFromBuild="false" action="copy">
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</file>
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<file path="./am243_am64_pru_pinmux.h" openOnCreation="false" excludeFromBuild="false" action="copy">
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</file>
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</project>
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</projectSpec>

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