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chore(linux): Update jacinto lpm doc
Add flow diagram, hardware details to excercise LPM mode. Signed-off-by: Udit Kumar <[email protected]>
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‎source/images/jacinto_s2r_entry.png‎

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‎source/images/jacinto_s2r_exit.png‎

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‎source/linux/Foundational_Components/Power_Management/pm_low_power_modes_socoff.rst‎

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@@ -8,18 +8,107 @@ Low power modes
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Overview
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********
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The following sections describe a high-level description of the different low power modes (LPM) supported on |__PART_FAMILY_NAME__| SoC (System on Chip).
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TI EVMs (Evaluation Modules) validate supported low power modes. Each mode needs evaluation based on power consumption and latency (the time it takes to wake-up to Active mode) requirements.
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There is a tradeoff between power and latency based on the mode. Users must select the appropriate low power mode at build time to fit the needs of the application. The default mode in the SDK is SoC off.
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A typical SoC, from power to HLOS (Linux here for example) takes around 20 seconds to boot (reaching till Linux prompt), when it is ready to
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run application.
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However, requirement is to run applications within 2-3 seconds of power-on. For this purpose, developers have implemented many custom optimizations,
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which do not scale from platform to platform.
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In SDK offering, following low power modes are supported:
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In LPM state, partial SW state saved to DDR that helps in achieving faster boot.
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#. SoC off
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#. I/O Only Plus DDR
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The following sections describe a high-level description of the different low power modes (LPM) supported on |__PART_FAMILY_DEVICE_NAMES__| SoC (System on Chip).
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+---------------------+---------------+---------------+-------------------------+-----------------------+
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| **Low power Mode** | **SoC State** | **DDR State** | **Retained SW context** | **Lost SW context** |
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+---------------------+---------------+---------------+-------------------------+-----------------------+
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| SOC OFF | Power off | Self Refresh | HLOS driver and apps | All fws (R5/M/C) core |
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+---------------------+---------------+---------------+-------------------------+-----------------------+
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| I/O only Plus DDR | Power off | Self Refresh | HLOS driver and apps | All fws (R5/M/C) core |
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| | except wakeup | | | |
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| | I/O | | | |
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+---------------------+---------------+---------------+-------------------------+-----------------------+
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Based upon the requirement of power consumption and latency (the time it takes to wake-up to Active mode),
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users can select the appropriate low power mode at **build time** to fit the needs of their application.
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The default mode in the SDK is **SOC OFF**.
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LPM entry overview
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==================
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After detecting the condition to enter standby, applications interacting with remote firmware shall be closed
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before entering standby.
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This section explains the high-level software flow of low power modes entry.
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.. image:: /images/jacinto_s2r_entry.png
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LPM exit overview
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=================
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On receiving wakeup trigger, PMIC will restore power to SoC and SoC resume process will exit DDR from self-refresh mode and restore the
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saved software context.
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As part of resume process, firmwares of remote cores will be reloaded, therefore application interacting with remote firmware shall be started again.
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This section explains the high-level software flow of low power modes exit.
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.. image:: /images/jacinto_s2r_exit.png
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*********************
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How to Test LPM modes
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*********************
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To test LPM modes, one needs to ensure that software and hardware configurations are correct.
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The following sections have details regarding the hardware and software configurations on TI EVMs.
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Hardware modifications
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======================
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.. ifconfig:: CONFIG_part_variant in ('J784S4')
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Following board modifications are needed to validate SOC_OFF and IO_ONLY_PLUS_DDR low power modes on the J784S4 EVM.
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- Change R534 from pull-down to pull-up to VCCA_3V3 side of C320, VDD_IO_1V8 powered down so that VDD1_DDR_1V8 also powers down unless EN remains high.
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- Remove R965, R1167, R1170, and R1169, During DDR RET, RESET must be pulled high.
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- R658 moved to R659
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.. ifconfig:: CONFIG_part_variant in ('J7200')
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By default, SOC_OFF mode can be validated on J7200 EVM without any hardware changes.
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In case IO_ONLY_PLUS_DDR mode needs to be tested,user needs to do the following board modification. These modifications will not impact SOC_OFF mode.
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- Remove R74 and place it at R610. This will pull the signal high.
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Software modifications
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======================
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TI’s K3 Jacinto family of SoCs have a concept of boardcfg that can be used to configure certain parameters at build time.
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By default, SOC_OFF mode enabled by default in SDK.
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IO_ONLY_PLUS_DDR mode can be enabled by changing boardcfg in u-boot at build time.
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The low power mode is set statically at build time in “lpm_cfg” section of the power management board config.
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In the u-boot source tree the boardcfg is present at:
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.. ifconfig:: CONFIG_part_variant in ('J7200')
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board/ti/j721e/pm-cfg_j7200.yaml
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`J7200 board config <https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/board/ti/j721e/pm-cfg_j7200.yaml?h=ti-u-boot-2025.01>`_ .
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.. ifconfig:: CONFIG_part_variant in ('J784S4')
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board/ti/j784s4/pm-cfg.yaml
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`J784s4 board config <https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/board/ti/j784s4/pm-cfg.yaml?h=ti-u-boot-2025.01>`_ .
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In above board config file, default lpm_mode is 0x5 (SOC_OFF) and suspend_initiator is 0xA (A72_0 host).
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To set the LPM mode as IO_RET_PLUS_DDR, change lpm_mode to 0x2.
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Sample code is available at
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https://gist.github.com/uditkumarti/fd0dfe8aa3dc094aadafecab67048307
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The lpm mode value can be picked up from:
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https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/lpm.html
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Testing
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=======
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Below section explains, how to test supported LPM modes
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*******
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SoC off
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*******
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-------
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In SoC off low power mode, DDR retains partial software context (Mainly HLOS - High Level Operating System, Linux in this case) powering off the rest of SoC. This can save a significant amount of boot time, because it does not reinitialize whole kernel as it is already present in DDR.
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Press SW15 push button on J784S4 evm.
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*****************
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I/O only Plus DDR
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*****************
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IO_ONLY_PLUS_DDR mode
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---------------------
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Use u-boot build after changing lpm_mode to 0x2, in boardconfig file.
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In I/O only plus DDR, only the I/O pins remain active while the system turns off the rest of SoC.
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#. Low power consumption: IO Only Plus DDR mode can save a significant amount of power, especially in battery-powered
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[ 41.416506] PM: suspend exit
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root@<machine>-evm:~#
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root@<machine>-evm:~#
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*****************
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Known limitations
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*****************
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1. Only A core as suspend master supported and tested with Linux.
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2. The LPM feature is not supported on HS-SE variant J784S4.
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3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected.
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4. Remote core firmwares are getting loaded by Linux on resume.
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5. MCU domain R5 core, cannot be used in split mode.

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