|
| 1 | +.. _how-to-enable-ssc-for-dss: |
| 2 | + |
| 3 | +############################################################ |
| 4 | +How to enable spread spectrum clocking for display subsystem |
| 5 | +############################################################ |
| 6 | + |
| 7 | +************ |
| 8 | +Introduction |
| 9 | +************ |
| 10 | + |
| 11 | +Spread Spectrum Clocking (SSC) is an electromagnetic interference (EMI) reduction technique that: |
| 12 | + |
| 13 | +- Modulates the clock frequency rather than keeping it constant |
| 14 | +- Varies the frequency over time in a controlled way |
| 15 | +- Spreads energy across many frequencies instead of focusing it at one frequency |
| 16 | +- Reduces peak emissions by spreading the electromagnetic energy |
| 17 | + |
| 18 | +This technique is common in electronic systems, especially in high-speed digital circuits. It helps meet EMI compliance without needing extra shielding or filters. |
| 19 | + |
| 20 | +Digital clock signals have a square wave shape. Most energy focuses at the center frequency and odd harmonics. In the frequency domain, SSC reduces the peak amplitude of the digital clock signal by spreading the energy across a wider frequency range. In the time domain, SSC adds jitter to the clock signal, but the voltage amplitude remains unchanged. |
| 21 | + |
| 22 | +Display Subsystem (DSS) supports SSC configuration for its pixel clocks through device tree properties. This helps you meet EMI compliance requirements. For DPI, DSS typically uses Phase-Locked Loop (PLL) 17. You can also use PLL 16 or PLL 18. |
| 23 | + |
| 24 | +This guide shows how to configure SSC for DSS pixel clocks on supported TI SoCs. |
| 25 | + |
| 26 | +.. important:: |
| 27 | + |
| 28 | + The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. When using center spread mode, calculate the highest peak frequency to ensure it stays under this limit: |
| 29 | + |
| 30 | + - For center spread: Highest frequency = Nominal frequency × (1 + (Modulation depth × 1.2) / 100) |
| 31 | + - For down spread: Highest frequency = Nominal frequency (no overshoot) |
| 32 | + |
| 33 | + Example: With 100 MHz nominal frequency and 0.5% modulation depth in center spread mode: |
| 34 | + |
| 35 | + - Highest frequency = 100 MHz × (1 + (0.5 × 1.2) / 100) = 100.6 MHz |
| 36 | + |
| 37 | + The 1.2 factor accounts for the 20% overshoot on the modulation depth in center spread mode. |
| 38 | + |
| 39 | +************************************************* |
| 40 | +Spread spectrum clocking configuration parameters |
| 41 | +************************************************* |
| 42 | + |
| 43 | +The ``assigned-clock-sscs`` device tree property configures SSC and takes three parameters: |
| 44 | + |
| 45 | ++-----------------------+----------------------------------------------------------------+ |
| 46 | +| Parameter | Description | |
| 47 | ++=======================+================================================================+ |
| 48 | +|| Modulation Frequency || The frequency at which the spread spectrum modulation occurs | |
| 49 | +|| (Hz) || - Minimum: 32,000 Hz (32 kHz) | |
| 50 | +|| || - Maximum: Reference clock frequency / 200 | |
| 51 | +|| || - Typical values: 32 kHz to 120 kHz | |
| 52 | ++-----------------------+----------------------------------------------------------------+ |
| 53 | +|| Modulation Depth || The amount of frequency spread as a percentage | |
| 54 | +|| || - Minimum: 10 (0.1%) | |
| 55 | +|| || - Maximum: 310 (3.1%) | |
| 56 | +|| || - Adjustable in increments of 10 (0.1%) | |
| 57 | +|| || - Example: 50 = 0.5% spread | |
| 58 | +|| || - Units: 1/10,000 (for example, 50 represents 0.5%) | |
| 59 | ++-----------------------+----------------------------------------------------------------+ |
| 60 | +|| Spread Type || - 1: Center spread (frequency varies on both higher and lower | |
| 61 | +|| || frequencies than nominal) | |
| 62 | +|| || - 3: Down spread (frequency varies only lower than nominal) | |
| 63 | ++-----------------------+----------------------------------------------------------------+ |
| 64 | + |
| 65 | +The modulation uses a triangular waveform. The Device Manager automatically configures the PLL hardware based on the parameters specified in the device tree. |
| 66 | + |
| 67 | +******** |
| 68 | +Examples |
| 69 | +******** |
| 70 | + |
| 71 | +Example 1: Basic SSC configuration (center spread) |
| 72 | +================================================== |
| 73 | + |
| 74 | +This example shows how to enable SSC for the DSS VP2 clock with the following parameters: |
| 75 | + |
| 76 | +- Modulation frequency: 100 kHz |
| 77 | +- Modulation depth: 10 (0.1%) |
| 78 | +- Spread type: Center spread (1) |
| 79 | + |
| 80 | +Add the following properties to the DSS node in your device tree file (for example, :file:`k3-am62p-j722s-common-main.dtsi`): |
| 81 | + |
| 82 | +.. code-block:: dts |
| 83 | +
|
| 84 | + &dss0 { |
| 85 | + assigned-clocks = <&k3_clks 186 2>; |
| 86 | + assigned-clock-sscs = <100000 10 1>; |
| 87 | + }; |
| 88 | +
|
| 89 | +.. warning:: |
| 90 | + |
| 91 | + This example uses center spread mode (1). Remember to apply the 1.2 factor for the 20% overshoot when calculating peak frequency. Consider down spread mode (Example 2) if you need to avoid exceeding the nominal frequency. |
| 92 | + |
| 93 | +Example 2: SSC with down spread mode |
| 94 | +==================================== |
| 95 | + |
| 96 | +This example demonstrates down spread mode, which we recommend for display interfaces: |
| 97 | + |
| 98 | +- Modulation frequency: 33 kHz |
| 99 | +- Modulation depth: 50 (0.5%) |
| 100 | +- Spread type: Down spread (3) |
| 101 | + |
| 102 | +.. code-block:: dts |
| 103 | +
|
| 104 | + &dss0 { |
| 105 | + assigned-clocks = <&k3_clks 186 2>; |
| 106 | + assigned-clock-sscs = <33000 50 3>; |
| 107 | + }; |
| 108 | +
|
| 109 | +Example 3: Greater modulation depth |
| 110 | +=================================== |
| 111 | + |
| 112 | +Here is a configuration with greater modulation depth for better EMI reduction: |
| 113 | + |
| 114 | +- Modulation frequency: 50 kHz |
| 115 | +- Modulation depth: 250 (2.5%) |
| 116 | +- Spread type: Down spread (3) |
| 117 | + |
| 118 | +.. code-block:: dts |
| 119 | +
|
| 120 | + &dss0 { |
| 121 | + assigned-clocks = <&k3_clks 186 2>; |
| 122 | + assigned-clock-sscs = <50000 250 3>; |
| 123 | + }; |
| 124 | +
|
| 125 | +*************** |
| 126 | +Troubleshooting |
| 127 | +*************** |
| 128 | + |
| 129 | +Display artifacts |
| 130 | +================= |
| 131 | + |
| 132 | +If you observe display artifacts, flickering, or other visual anomalies after enabling SSC: |
| 133 | + |
| 134 | +1. Reduce the modulation depth to a smaller value (for example, try 0.1% or 10 in device tree) |
| 135 | +2. Try a different modulation frequency (typical range: 32-100 kHz) |
| 136 | +3. Switch from center spread to down spread mode if not already using it |
| 137 | +4. Consult your display panel data sheet for spread spectrum tolerance specifications |
| 138 | + |
| 139 | +Clock not found error |
| 140 | +===================== |
| 141 | + |
| 142 | +If you experience errors during boot about clock assignment: |
| 143 | + |
| 144 | +1. Verify the clock ID is correct for your SoC (check the technical reference manual) |
| 145 | +2. Ensure the Device Manager supports SSC for the specified clock |
| 146 | +3. Check that the kernel version includes SSC support for the clock subsystem |
| 147 | + |
| 148 | +**************************** |
| 149 | +Requirements and limitations |
| 150 | +**************************** |
| 151 | + |
| 152 | +**Hardware support:** |
| 153 | + |
| 154 | +- SSC is currently supported only on display PLL for these SoCs: AM62x, AM62Ax, AM62Dx, AM62Px |
| 155 | +- The display PLL is typically PLL 17. You can also use PLL 16 or PLL 18 for DPI applications |
| 156 | + |
| 157 | +**Configuration:** |
| 158 | + |
| 159 | +- Configure SSC together with ``assigned-clocks`` and ``assigned-clock-sscs`` to specify which clock receives the SSC settings |
| 160 | +- SSC causes the instantaneous clock frequency to deviate from the nominal rate |
| 161 | +- Some panels have strict jitter requirements |
| 162 | + |
| 163 | +**Firmware capability:** |
| 164 | + |
| 165 | +Check if your firmware supports SSC by using the capability flag: |
| 166 | + |
| 167 | +.. code-block:: console |
| 168 | +
|
| 169 | + # Check firmware capabilities (requires ti-sci driver) |
| 170 | + cat /sys/kernel/debug/ti-sci/fw_caps |
| 171 | +
|
| 172 | +Look for ``TISCI_MSG_FLAG_FW_CAP_CLOCK_SSC`` in the capabilities list. |
| 173 | + |
| 174 | +********************************** |
| 175 | +Best practices and recommendations |
| 176 | +********************************** |
| 177 | + |
| 178 | +- Start with low modulation depth (0.1% to 0.5%) and increase only if needed |
| 179 | +- Use down spread mode (3) for display interfaces to ensure the clock never exceeds the specified maximum frequency |
| 180 | +- Apply the 1.2 factor when using center spread mode |
| 181 | +- Validate configuration with your display panel to ensure timing margins meet requirements |
| 182 | + |
| 183 | +************************* |
| 184 | +Customer responsibilities |
| 185 | +************************* |
| 186 | + |
| 187 | +.. warning:: |
| 188 | + |
| 189 | + **You assume all responsibility for the configuration and usage of spread spectrum clocking.** You must: |
| 190 | + |
| 191 | + 1. Research the clock limitations associated with your selected display panel |
| 192 | + 2. Configure SSC to be compatible with that specific display panel |
| 193 | + 3. Verify that the SSC configuration does not cause any system-related issues for any operating condition |
| 194 | + 4. Work with the display panel vendor to resolve any issues caused by enabling SSC |
| 195 | + 5. Validate displays to have enough functional margin with the jitter introduced by spread spectrum modulation |
| 196 | + |
| 197 | + Some display panels have clocking limitations not mentioned in their data sheets. Work directly with the display panel manufacturer on any display-related issues from SSC. |
| 198 | + |
| 199 | +********** |
| 200 | +References |
| 201 | +********** |
| 202 | + |
| 203 | +- :ref:`dss7` |
| 204 | +- SoC Technical Reference Manual (TRM) |
| 205 | +- System Firmware Documentation - PM Clock API |
| 206 | +- Linux kernel device tree bindings: ``Documentation/devicetree/bindings/display/ti/`` |
| 207 | +- Linux kernel clock framework documentation: ``Documentation/driver-api/clk.rst`` |
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