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Neha Malcom Francisuditkumarti
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feat(linux): Add guide on triggering BIST
Add a How-To Guide for triggering BIST on a core from A72 SPL. Signed-off-by: Neha Malcom Francis <[email protected]>
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‎configs/J784S4/J784S4_linux_toc.txt‎

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@@ -133,4 +133,5 @@ linux/How_to_Guides/Host/How_to_Build_a_Ubuntu_Linux_host_under_VMware
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linux/How_to_Guides_Hardware_Setup_with_CCS
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linux/How_to_Guides/Hardware_Setup_with_CCS/J784S4_EVM_Hardware_Setup
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linux/How_to_Guides/Hardware_Setup_with_CCS/AM69_SK_EVM_Hardware_Setup
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linux/How_to_Guides/FAQ/How_to_run_BIST_on_a_core
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linux/Documentation_Tarball

‎source/linux/How_to_Guides/FAQ/How_to_run_BIST_on_a_core.rst‎

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##############################
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How to trigger BIST on a core?
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##############################
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Built-in Self-test (BIST) is a feature that allows self testing of the memory
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areas and logic circuitry in an Integrated Circuit (IC) without any external
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test equipment. In an embedded system, these tests are typically used during
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boot time or shutdown of the system to check the health of an SoC.
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PBIST is used to test the memory regions in the SoC and provides detection for
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permanent faults. The primary use case for PBIST is when it is invoked at
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start-up providing valuable information on any stuck-at bits in the memory.
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LBIST is used to test the logic circuitry in an SoC associated with the CPU
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cores. There are multiple LBIST instances in the SoC, and each has a different
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processor core associated with it. There are LBIST tests that can be
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software-initiated.
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- Current implementation triggers the BIST tests on the MAIN_R5_2_x cores.
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- LBIST/PBIST checks of the WKUP_DMSC0 and MCU_R5FSS0 cores and memories are
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run in the WKUP/MCU domain; this check is part of HW POST. HW POST runs in
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hardware, before the ROM code starts and can be selected by MCU_BOOTMODE[09:08]
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pins.
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*********************************
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Steps to trigger BIST from U-Boot
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*********************************
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- Enable the BIST config at A72 SPL stage:
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.. code-block:: diff
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diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig
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index 52d12b6206b..1d2b4c3262f 100644
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--- a/configs/j784s4_evm_a72_defconfig
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+++ b/configs/j784s4_evm_a72_defconfig
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@@ -1,3 +1,4 @@
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+CONFIG_K3_BIST=y
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CONFIG_ARM=y
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CONFIG_ARCH_K3=y
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CONFIG_SYS_MALLOC_LEN=0x2000000
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- Debug logs may be enabled if needed:
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.. code-block:: diff
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diff --git a/drivers/misc/k3_bist.c b/drivers/misc/k3_bist.c
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index fd3140add68..6668de93ab2 100644
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--- a/drivers/misc/k3_bist.c
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+++ b/drivers/misc/k3_bist.c
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@@ -6,7 +6,7 @@
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* Neha Malcom Francis <[email protected]>
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*
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*/
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-
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+#define LOG_DEBUG
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#include <dm.h>
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#include <errno.h>
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#include <clk.h>
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- Rebuild A72 SPL image (tispl.bin) with the above changes to enable BIST tests
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to run on a particular core.
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- While booting to the U-Boot prompt, your prints should be similar to the log
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below:
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.. code-block:: console
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U-Boot SPL 2025.01-00253-g9a3137c5c11a-dirty (Feb 28 2025 - 09:48:36 +0530)
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SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
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Initialized 4 DRAM controllers
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SPL initial stack usage: 13440 bytes
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Trying to boot from MMC2
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Skipping authentication on GP device
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Skipping authentication on GP device
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Skipping authentication on GP device
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Skipping authentication on GP device
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Skipping authentication on GP device
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Loading Environment from nowhere... OK
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Starting ATF on ARM64 core...
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NOTICE: BL31: v2.12.0(release):5227171c0-dirty
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NOTICE: BL31: Built : 13:45:40, Feb 3 2025
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I/TC:
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I/TC: OP-TEE version: 4.5.0-73-gef1ebdc23-dev (gcc version 13.3.0 (GCC)) #1 Tue Feb 4 11:33:18 UTC 2025 aarch64
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I/TC: WARNING: This OP-TEE configuration might be insecure!
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I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
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I/TC: Primary CPU initializing
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I/TC: GIC redistributor base address not provided
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I/TC: Assuming default GIC group status and modifier
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I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
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I/TC: Activated SA2UL device
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I/TC: Fixing SA2UL firewall owner for GP device
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I/TC: Enabled firewalls for SA2UL TRNG device
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I/TC: SA2UL TRNG initialized
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I/TC: SA2UL Drivers initialized
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I/TC: HUK Initialized
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I/TC: Primary CPU switching to normal world boot
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U-Boot SPL 2025.01-00253-g9a3137c5c11a-dirty (Feb 28 2025 - 09:48:54 +0530)
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SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
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k3_bist_probe(dev=8047a548)
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check_post_pbist_result: HW POST PBIST completed, test passed
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check_post_lbist_result: HW POST LBIST completed, test passed
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lbist_start(dev=8047a548): LBIST is running
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Trying to boot from MMC2
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Skipping authentication on GP device
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Skipping authentication on GP device
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U-Boot 2025.01-00253-g9a3137c5c11a-dirty (Feb 28 2025 - 09:48:54 +0530)
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SoC: J784S4 SR1.0 GP
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Model: Texas Instruments J784S4 EVM
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DRAM: 2 GiB (effective 32 GiB)
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Core: 143 devices, 35 uclasses, devicetree: separate
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Flash: 0 Bytes
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MMC: mmc@4f80000: 0, mmc@4fb0000: 1
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Loading Environment from nowhere... OK
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In: serial@2880000
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Out: serial@2880000
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Err: serial@2880000
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am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
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Net: eth0: ethernet@46000000port@1
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Hit any key to stop autoboot: 0
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=>
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- Run and load firmware on the core as usual:
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.. code-block:: console
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=> rproc init
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k3_r5f_rproc r5f@41000000: Core 1 is already in use. No rproc commands work
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k3_r5f_rproc r5f@41400000: Core 2 is already in use. No rproc commands work
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=> load mmc 1:2 0x90000000 /lib/firmware/j784s4-main-r5f2_0-fw
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80600 bytes read in 37 ms (2.1 MiB/s)
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=> rproc load 6 0x90000000 0x${filesize}
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Load Remote Processor 6 with data@addr=0x90000000 80600 bytes: Success!
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=> rproc start 6
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=>

‎source/linux/How_to_Guides_Developer_Notes.rst‎

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How_to_Guides/Host/Minimal_Platform_Development
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How_to_Guides/Host/Program_MMC_boot_media
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How_to_Guides/FAQ/Tda4_Latest_FAQs
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How_to_Guides/FAQ/How_to_run_BIST_on_a_core

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