Skip to content

Commit edce1d4

Browse files
uditkumartiuditkumarti
committed
chore(linux): Update jacinto lpm doc
Add flow diagram, hardware details to excercise LPM mode. Signed-off-by: Udit Kumar <[email protected]>
1 parent 6bb8848 commit edce1d4

File tree

3 files changed

+110
-12
lines changed

3 files changed

+110
-12
lines changed

‎source/images/jacinto_s2r_entry.png‎

37.6 KB
Loading

‎source/images/jacinto_s2r_exit.png‎

30 KB
Loading

‎source/linux/Foundational_Components/Power_Management/pm_low_power_modes_socoff.rst‎

Lines changed: 110 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,18 +8,106 @@ Low power modes
88
Overview
99
********
1010

11-
The following sections describe a high-level description of the different low power modes (LPM) supported on |__PART_FAMILY_NAME__| SoC (System on Chip).
12-
TI EVMs (Evaluation Modules) validate supported low power modes. Each mode needs evaluation based on power consumption and latency (the time it takes to wake-up to Active mode) requirements.
13-
There is a tradeoff between power and latency based on the mode. Users must select the appropriate low power mode at build time to fit the needs of the application. The default mode in the SDK is SoC off.
11+
A typical SOC, from power to HLOS (Linux here for example) takes around 20 seconds to boot (ie reaching till Linux prompt), when it’s ready to
12+
run application.
13+
However, it is desired to run application use cases within 2-3 seconds of power on, for this purpose there are many custom
14+
optimizations done, which are not scalable from platform to platform.
15+
LPM saves partially SW state to DDR which helps in achieving faster boot.
16+
17+
The following sections describe a high-level description of the different low power modes (LPM) supported on |__PART_FAMILY_DEVICE_NAMES__| SoC (System on Chip).
18+
19+
+---------------------+---------------+---------------+-------------------------+-----------------------+
20+
| **Low power Mode** | **SOC State** | **DDR State** | **Retained SW context** | **Lost SW context** |
21+
+---------------------+---------------+---------------+-------------------------+-----------------------+
22+
| SOC OFF | Power off | Self Refresh | HLOS driver and apps | All fws (R5/M/C) core |
23+
+---------------------+---------------+---------------+-------------------------+-----------------------+
24+
| I/O only Plus DDR | Power off | Self Refresh | HLOS driver and apps | All fws (R5/M/C) core |
25+
| | except wakeup | | | |
26+
| | I/O | | | |
27+
+---------------------+---------------+---------------+-------------------------+-----------------------+
28+
29+
Based upon, requirement of on power consumption and latency (the time it takes to wake-up to Active mode).
30+
User can select the appropriate low power mode at **build time** to fit the needs of the application.
31+
The default mode in the SDK is **SOC OFF**.
32+
33+
------------------
34+
LPM entry overview
35+
------------------
36+
After detecting condition to enter into standby, Application shall close all applications interacting with
37+
remote firmwares, proceed to enter into standby.
38+
This section explains the high-level software flow of low power modes entry.
39+
40+
.. image:: /images/jacinto_s2r_entry.png
41+
42+
-----------------
43+
LPM exit overview
44+
-----------------
45+
On receiving wakeup trigger, PMIC will restore power to SOC and SOC resume process will exit DDR from self-refresh mode and restore the
46+
saved software context.
47+
As part of resume process, firmwares of remote cores will be reloaded, Therefore application interacting with remote firmware shall be started again.
48+
This section explains the high-level software flow of low power modes exit.
49+
50+
.. image:: /images/jacinto_s2r_exit.png
51+
52+
53+
*********************
54+
How to Test LPM modes
55+
*********************
56+
To test LPM modes, one needs to ensure that software and hardware configurations are correct.
57+
The following sections have details regarding the hardware and software configurations on TI EVMs.
58+
59+
----------------------
60+
Hardware modifications
61+
----------------------
1462

15-
In SDK offering, following low power modes are supported:
63+
.. ifconfig:: CONFIG_part_variant in ('J784S4')
64+
65+
Following board modifications are needed to validate SOC_OFF and IO_ONLY_PLUS_DDR low power modes on the J784S4 EVM.
66+
67+
- Change R534 from pull-down to pull-up to VCCA_3V3 side of C320, VDD_IO_1V8 powered down so that VDD1_DDR_1V8 also powers down unless EN remains high.
68+
- Remove R965, R1167, R1170, and R1169, During DDR RET, RESET must be pulled high.
69+
- R658 moved to R659
70+
71+
.. ifconfig:: CONFIG_part_variant in ('J7200')
72+
73+
By default, SOC_OFF mode can be validated on J7200 EVM without any hardware changes.
74+
In case IO_ONLY_PLUS_DDR needs to be tested user needs to do the following board modification. These modifications will not impact SOC_OFF mode.
1675

17-
#. SoC off
18-
#. I/O Only Plus DDR
76+
- Remove R74 and place it at R610. This will pull the signal high.
1977

20-
*******
21-
SoC off
22-
*******
78+
----------------------
79+
Software modifications
80+
----------------------
81+
TI’s K3 Jacinto family of SOCs have a concept of boardcfg that can be used to configure certain parameters at build time.
82+
By default, SDK supports SOC_OFF mode.
83+
IO_ONLY_PLUS_DDR mode will be enabled by changing boardcfg in u-boot at build time.
84+
85+
The low power mode is set statically at build time in “lpm_cfg” section of the power management board config.
86+
In the u-boot source tree the boardcfg is present at:
87+
88+
.. ifconfig:: CONFIG_part_variant in ('J7200')
89+
90+
board/ti/j721e/pm-cfg_j7200.yaml
91+
`J7200 board config <https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/board/ti/j721e/pm-cfg_j7200.yaml?h=ti-u-boot-2025.01>`_ .
92+
93+
.. ifconfig:: CONFIG_part_variant in ('J784S4')
94+
95+
board/ti/j784s4/pm-cfg.yaml
96+
`J784s4 board config <https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/board/ti/j784s4/pm-cfg.yaml?h=ti-u-boot-2025.01>`_ .
97+
98+
In above board config file, default lpm_mode is 0x5 (SOC_OFF) and suspend_initiator is 0xA (A72_0 host).
99+
100+
To set the LPM mode as IO_RET_PLUS_DDR. Change lpm_mode to 0x2
101+
102+
Sample code is available at
103+
https://gist.github.com/uditkumarti/fd0dfe8aa3dc094aadafecab67048307
104+
105+
The lpm mode value can be picked up from:
106+
https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/pm/lpm.html
107+
108+
---------------
109+
Testing SoC off
110+
---------------
23111

24112
In SoC off low power mode, DDR retains partial software context (Mainly HLOS - High Level Operating System, Linux in this case) powering off the rest of SoC. This can save a significant amount of boot time, because it does not reinitialize whole kernel as it is already present in DDR.
25113

@@ -57,10 +145,11 @@ To exit from SoC off,
57145
Press SW15 push button on J784S4 evm.
58146

59147

60-
*****************
61-
I/O only Plus DDR
62-
*****************
148+
----------------------------
149+
Tesing IO_ONLY_PLUS_DDR mode
150+
----------------------------
63151

152+
Use u-boot build after changing lpm_mode to 0x2, in boardconfig file.
64153
In I/O only plus DDR, only the I/O pins remain active while the system turns off the rest of SoC.
65154

66155
#. Low power consumption: IO Only Plus DDR mode can save a significant amount of power, especially in battery-powered
@@ -143,3 +232,12 @@ Resume flow,
143232
[ 41.416506] PM: suspend exit
144233
root@<machine>-evm:~#
145234
root@<machine>-evm:~#
235+
236+
*****************
237+
Known limitations
238+
*****************
239+
1. Only A core as suspend master supported and tested with Linux.
240+
2. The LPM feature is not supported on HS-SE variant J784S4.
241+
3. If PCIe is being used, the resume latency increases by 1 sec for every PCIe instance, If EP is not connected.
242+
4. Remote core firmwares are getting loaded by Linux on resume.
243+
5. MCU domain R5 core, cannot be used in split mode.

0 commit comments

Comments
 (0)