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3606 lines (3372 loc) · 141 KB
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//
// Generated by Bluespec Compiler, version 2014.07.A (build 34078, 2014-07-30)
//
// On Wed Jul 4 23:58:12 -03 2018
//
//
// Ports:
// Name I/O size props
// RDY_initialize O 1 const
// RDY_run O 1
// get O 192 reg
// RDY_get O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// initialize_s1 I 32
// initialize_s2 I 32
// run_val I 64 reg
// EN_initialize I 1
// EN_run I 1
// EN_get I 1 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkBoxMuller(CLK,
RST_N,
initialize_s1,
initialize_s2,
EN_initialize,
RDY_initialize,
run_val,
EN_run,
RDY_run,
EN_get,
get,
RDY_get);
input CLK;
input RST_N;
// action method initialize
input [31 : 0] initialize_s1;
input [31 : 0] initialize_s2;
input EN_initialize;
output RDY_initialize;
// action method run
input [63 : 0] run_val;
input EN_run;
output RDY_run;
// actionvalue method get
input EN_get;
output [191 : 0] get;
output RDY_get;
// signals for module outputs
wire [191 : 0] get;
wire RDY_get, RDY_initialize, RDY_run;
// inlined wires
wire testFSM_start_wire$whas, testFSM_state_set_pw$whas;
// register cycle
reg [31 : 0] cycle;
wire [31 : 0] cycle$D_IN;
wire cycle$EN;
// register flag
reg flag;
wire flag$D_IN, flag$EN;
// register r1
reg [64 : 0] r1;
wire [64 : 0] r1$D_IN;
wire r1$EN;
// register r2
reg [64 : 0] r2;
wire [64 : 0] r2$D_IN;
wire r2$EN;
// register randtuple
reg [191 : 0] randtuple;
wire [191 : 0] randtuple$D_IN;
wire randtuple$EN;
// register testFSM_start_reg
reg testFSM_start_reg;
wire testFSM_start_reg$D_IN, testFSM_start_reg$EN;
// register testFSM_start_reg_1
reg testFSM_start_reg_1;
wire testFSM_start_reg_1$D_IN, testFSM_start_reg_1$EN;
// register testFSM_state_can_overlap
reg testFSM_state_can_overlap;
wire testFSM_state_can_overlap$D_IN, testFSM_state_can_overlap$EN;
// register testFSM_state_fired
reg testFSM_state_fired;
wire testFSM_state_fired$D_IN, testFSM_state_fired$EN;
// register testFSM_state_mkFSMstate
reg [2 : 0] testFSM_state_mkFSMstate;
reg [2 : 0] testFSM_state_mkFSMstate$D_IN;
wire testFSM_state_mkFSMstate$EN;
// register v1
reg [31 : 0] v1;
wire [31 : 0] v1$D_IN;
wire v1$EN;
// register v2
reg [31 : 0] v2;
wire [31 : 0] v2$D_IN;
wire v2$EN;
// register valsqrIn
reg [63 : 0] valsqrIn;
wire [63 : 0] valsqrIn$D_IN;
wire valsqrIn$EN;
// register valsqrOut
reg [63 : 0] valsqrOut;
wire [63 : 0] valsqrOut$D_IN;
wire valsqrOut$EN;
// register x_1
reg [64 : 0] x_1;
wire [64 : 0] x_1$D_IN;
wire x_1$EN;
// register x_2
reg [64 : 0] x_2;
wire [64 : 0] x_2$D_IN;
wire x_2$EN;
// ports of submodule fCheck
wire [63 : 0] fCheck$D_IN;
wire fCheck$CLR, fCheck$DEQ, fCheck$ENQ;
// ports of submodule mLUT
wire [64 : 0] mLUT$run_input_val;
wire mLUT$EN_get, mLUT$EN_run;
// ports of submodule rgn1
wire [31 : 0] rgn1$get, rgn1$initialize_s;
wire rgn1$EN_get, rgn1$EN_initialize;
// ports of submodule rgn2
wire [31 : 0] rgn2$get, rgn2$initialize_s;
wire rgn2$EN_get, rgn2$EN_initialize;
// ports of submodule sqrtfxm_fRequest
wire [63 : 0] sqrtfxm_fRequest$D_IN, sqrtfxm_fRequest$D_OUT;
wire sqrtfxm_fRequest$CLR,
sqrtfxm_fRequest$DEQ,
sqrtfxm_fRequest$EMPTY_N,
sqrtfxm_fRequest$ENQ,
sqrtfxm_fRequest$FULL_N;
// ports of submodule sqrtfxm_fResponse
wire [64 : 0] sqrtfxm_fResponse$D_IN, sqrtfxm_fResponse$D_OUT;
wire sqrtfxm_fResponse$CLR,
sqrtfxm_fResponse$DEQ,
sqrtfxm_fResponse$EMPTY_N,
sqrtfxm_fResponse$ENQ,
sqrtfxm_fResponse$FULL_N;
// ports of submodule sqrtfxm_fShift
wire [6 : 0] sqrtfxm_fShift$D_IN, sqrtfxm_fShift$D_OUT;
wire sqrtfxm_fShift$CLR,
sqrtfxm_fShift$DEQ,
sqrtfxm_fShift$EMPTY_N,
sqrtfxm_fShift$ENQ,
sqrtfxm_fShift$FULL_N;
// ports of submodule sqrtfxm_sqrt_fFirst
wire [256 : 0] sqrtfxm_sqrt_fFirst$D_IN, sqrtfxm_sqrt_fFirst$D_OUT;
wire sqrtfxm_sqrt_fFirst$CLR,
sqrtfxm_sqrt_fFirst$DEQ,
sqrtfxm_sqrt_fFirst$EMPTY_N,
sqrtfxm_sqrt_fFirst$ENQ,
sqrtfxm_sqrt_fFirst$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_0
wire [256 : 0] sqrtfxm_sqrt_fNext_0$D_IN, sqrtfxm_sqrt_fNext_0$D_OUT;
wire sqrtfxm_sqrt_fNext_0$CLR,
sqrtfxm_sqrt_fNext_0$DEQ,
sqrtfxm_sqrt_fNext_0$EMPTY_N,
sqrtfxm_sqrt_fNext_0$ENQ,
sqrtfxm_sqrt_fNext_0$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_1
wire [256 : 0] sqrtfxm_sqrt_fNext_1$D_IN, sqrtfxm_sqrt_fNext_1$D_OUT;
wire sqrtfxm_sqrt_fNext_1$CLR,
sqrtfxm_sqrt_fNext_1$DEQ,
sqrtfxm_sqrt_fNext_1$EMPTY_N,
sqrtfxm_sqrt_fNext_1$ENQ,
sqrtfxm_sqrt_fNext_1$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_10
wire [256 : 0] sqrtfxm_sqrt_fNext_10$D_IN, sqrtfxm_sqrt_fNext_10$D_OUT;
wire sqrtfxm_sqrt_fNext_10$CLR,
sqrtfxm_sqrt_fNext_10$DEQ,
sqrtfxm_sqrt_fNext_10$EMPTY_N,
sqrtfxm_sqrt_fNext_10$ENQ,
sqrtfxm_sqrt_fNext_10$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_11
wire [256 : 0] sqrtfxm_sqrt_fNext_11$D_IN, sqrtfxm_sqrt_fNext_11$D_OUT;
wire sqrtfxm_sqrt_fNext_11$CLR,
sqrtfxm_sqrt_fNext_11$DEQ,
sqrtfxm_sqrt_fNext_11$EMPTY_N,
sqrtfxm_sqrt_fNext_11$ENQ,
sqrtfxm_sqrt_fNext_11$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_12
wire [256 : 0] sqrtfxm_sqrt_fNext_12$D_IN, sqrtfxm_sqrt_fNext_12$D_OUT;
wire sqrtfxm_sqrt_fNext_12$CLR,
sqrtfxm_sqrt_fNext_12$DEQ,
sqrtfxm_sqrt_fNext_12$EMPTY_N,
sqrtfxm_sqrt_fNext_12$ENQ,
sqrtfxm_sqrt_fNext_12$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_13
wire [256 : 0] sqrtfxm_sqrt_fNext_13$D_IN, sqrtfxm_sqrt_fNext_13$D_OUT;
wire sqrtfxm_sqrt_fNext_13$CLR,
sqrtfxm_sqrt_fNext_13$DEQ,
sqrtfxm_sqrt_fNext_13$EMPTY_N,
sqrtfxm_sqrt_fNext_13$ENQ,
sqrtfxm_sqrt_fNext_13$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_14
wire [256 : 0] sqrtfxm_sqrt_fNext_14$D_IN, sqrtfxm_sqrt_fNext_14$D_OUT;
wire sqrtfxm_sqrt_fNext_14$CLR,
sqrtfxm_sqrt_fNext_14$DEQ,
sqrtfxm_sqrt_fNext_14$EMPTY_N,
sqrtfxm_sqrt_fNext_14$ENQ,
sqrtfxm_sqrt_fNext_14$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_15
wire [256 : 0] sqrtfxm_sqrt_fNext_15$D_IN, sqrtfxm_sqrt_fNext_15$D_OUT;
wire sqrtfxm_sqrt_fNext_15$CLR,
sqrtfxm_sqrt_fNext_15$DEQ,
sqrtfxm_sqrt_fNext_15$EMPTY_N,
sqrtfxm_sqrt_fNext_15$ENQ,
sqrtfxm_sqrt_fNext_15$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_16
wire [256 : 0] sqrtfxm_sqrt_fNext_16$D_IN, sqrtfxm_sqrt_fNext_16$D_OUT;
wire sqrtfxm_sqrt_fNext_16$CLR,
sqrtfxm_sqrt_fNext_16$DEQ,
sqrtfxm_sqrt_fNext_16$EMPTY_N,
sqrtfxm_sqrt_fNext_16$ENQ,
sqrtfxm_sqrt_fNext_16$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_17
wire [256 : 0] sqrtfxm_sqrt_fNext_17$D_IN, sqrtfxm_sqrt_fNext_17$D_OUT;
wire sqrtfxm_sqrt_fNext_17$CLR,
sqrtfxm_sqrt_fNext_17$DEQ,
sqrtfxm_sqrt_fNext_17$EMPTY_N,
sqrtfxm_sqrt_fNext_17$ENQ,
sqrtfxm_sqrt_fNext_17$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_18
wire [256 : 0] sqrtfxm_sqrt_fNext_18$D_IN, sqrtfxm_sqrt_fNext_18$D_OUT;
wire sqrtfxm_sqrt_fNext_18$CLR,
sqrtfxm_sqrt_fNext_18$DEQ,
sqrtfxm_sqrt_fNext_18$EMPTY_N,
sqrtfxm_sqrt_fNext_18$ENQ,
sqrtfxm_sqrt_fNext_18$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_19
wire [256 : 0] sqrtfxm_sqrt_fNext_19$D_IN, sqrtfxm_sqrt_fNext_19$D_OUT;
wire sqrtfxm_sqrt_fNext_19$CLR,
sqrtfxm_sqrt_fNext_19$DEQ,
sqrtfxm_sqrt_fNext_19$EMPTY_N,
sqrtfxm_sqrt_fNext_19$ENQ,
sqrtfxm_sqrt_fNext_19$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_2
wire [256 : 0] sqrtfxm_sqrt_fNext_2$D_IN, sqrtfxm_sqrt_fNext_2$D_OUT;
wire sqrtfxm_sqrt_fNext_2$CLR,
sqrtfxm_sqrt_fNext_2$DEQ,
sqrtfxm_sqrt_fNext_2$EMPTY_N,
sqrtfxm_sqrt_fNext_2$ENQ,
sqrtfxm_sqrt_fNext_2$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_20
wire [256 : 0] sqrtfxm_sqrt_fNext_20$D_IN, sqrtfxm_sqrt_fNext_20$D_OUT;
wire sqrtfxm_sqrt_fNext_20$CLR,
sqrtfxm_sqrt_fNext_20$DEQ,
sqrtfxm_sqrt_fNext_20$EMPTY_N,
sqrtfxm_sqrt_fNext_20$ENQ,
sqrtfxm_sqrt_fNext_20$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_21
wire [256 : 0] sqrtfxm_sqrt_fNext_21$D_IN, sqrtfxm_sqrt_fNext_21$D_OUT;
wire sqrtfxm_sqrt_fNext_21$CLR,
sqrtfxm_sqrt_fNext_21$DEQ,
sqrtfxm_sqrt_fNext_21$EMPTY_N,
sqrtfxm_sqrt_fNext_21$ENQ,
sqrtfxm_sqrt_fNext_21$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_22
wire [256 : 0] sqrtfxm_sqrt_fNext_22$D_IN, sqrtfxm_sqrt_fNext_22$D_OUT;
wire sqrtfxm_sqrt_fNext_22$CLR,
sqrtfxm_sqrt_fNext_22$DEQ,
sqrtfxm_sqrt_fNext_22$EMPTY_N,
sqrtfxm_sqrt_fNext_22$ENQ,
sqrtfxm_sqrt_fNext_22$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_23
wire [256 : 0] sqrtfxm_sqrt_fNext_23$D_IN, sqrtfxm_sqrt_fNext_23$D_OUT;
wire sqrtfxm_sqrt_fNext_23$CLR,
sqrtfxm_sqrt_fNext_23$DEQ,
sqrtfxm_sqrt_fNext_23$EMPTY_N,
sqrtfxm_sqrt_fNext_23$ENQ,
sqrtfxm_sqrt_fNext_23$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_24
wire [256 : 0] sqrtfxm_sqrt_fNext_24$D_IN, sqrtfxm_sqrt_fNext_24$D_OUT;
wire sqrtfxm_sqrt_fNext_24$CLR,
sqrtfxm_sqrt_fNext_24$DEQ,
sqrtfxm_sqrt_fNext_24$EMPTY_N,
sqrtfxm_sqrt_fNext_24$ENQ,
sqrtfxm_sqrt_fNext_24$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_25
wire [256 : 0] sqrtfxm_sqrt_fNext_25$D_IN, sqrtfxm_sqrt_fNext_25$D_OUT;
wire sqrtfxm_sqrt_fNext_25$CLR,
sqrtfxm_sqrt_fNext_25$DEQ,
sqrtfxm_sqrt_fNext_25$EMPTY_N,
sqrtfxm_sqrt_fNext_25$ENQ,
sqrtfxm_sqrt_fNext_25$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_26
wire [256 : 0] sqrtfxm_sqrt_fNext_26$D_IN, sqrtfxm_sqrt_fNext_26$D_OUT;
wire sqrtfxm_sqrt_fNext_26$CLR,
sqrtfxm_sqrt_fNext_26$DEQ,
sqrtfxm_sqrt_fNext_26$EMPTY_N,
sqrtfxm_sqrt_fNext_26$ENQ,
sqrtfxm_sqrt_fNext_26$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_27
wire [256 : 0] sqrtfxm_sqrt_fNext_27$D_IN, sqrtfxm_sqrt_fNext_27$D_OUT;
wire sqrtfxm_sqrt_fNext_27$CLR,
sqrtfxm_sqrt_fNext_27$DEQ,
sqrtfxm_sqrt_fNext_27$EMPTY_N,
sqrtfxm_sqrt_fNext_27$ENQ,
sqrtfxm_sqrt_fNext_27$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_28
wire [256 : 0] sqrtfxm_sqrt_fNext_28$D_IN, sqrtfxm_sqrt_fNext_28$D_OUT;
wire sqrtfxm_sqrt_fNext_28$CLR,
sqrtfxm_sqrt_fNext_28$DEQ,
sqrtfxm_sqrt_fNext_28$EMPTY_N,
sqrtfxm_sqrt_fNext_28$ENQ,
sqrtfxm_sqrt_fNext_28$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_29
wire [256 : 0] sqrtfxm_sqrt_fNext_29$D_IN, sqrtfxm_sqrt_fNext_29$D_OUT;
wire sqrtfxm_sqrt_fNext_29$CLR,
sqrtfxm_sqrt_fNext_29$DEQ,
sqrtfxm_sqrt_fNext_29$EMPTY_N,
sqrtfxm_sqrt_fNext_29$ENQ,
sqrtfxm_sqrt_fNext_29$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_3
wire [256 : 0] sqrtfxm_sqrt_fNext_3$D_IN, sqrtfxm_sqrt_fNext_3$D_OUT;
wire sqrtfxm_sqrt_fNext_3$CLR,
sqrtfxm_sqrt_fNext_3$DEQ,
sqrtfxm_sqrt_fNext_3$EMPTY_N,
sqrtfxm_sqrt_fNext_3$ENQ,
sqrtfxm_sqrt_fNext_3$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_30
wire [256 : 0] sqrtfxm_sqrt_fNext_30$D_IN, sqrtfxm_sqrt_fNext_30$D_OUT;
wire sqrtfxm_sqrt_fNext_30$CLR,
sqrtfxm_sqrt_fNext_30$DEQ,
sqrtfxm_sqrt_fNext_30$EMPTY_N,
sqrtfxm_sqrt_fNext_30$ENQ,
sqrtfxm_sqrt_fNext_30$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_31
wire [256 : 0] sqrtfxm_sqrt_fNext_31$D_IN, sqrtfxm_sqrt_fNext_31$D_OUT;
wire sqrtfxm_sqrt_fNext_31$CLR,
sqrtfxm_sqrt_fNext_31$DEQ,
sqrtfxm_sqrt_fNext_31$EMPTY_N,
sqrtfxm_sqrt_fNext_31$ENQ,
sqrtfxm_sqrt_fNext_31$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_32
wire [256 : 0] sqrtfxm_sqrt_fNext_32$D_IN, sqrtfxm_sqrt_fNext_32$D_OUT;
wire sqrtfxm_sqrt_fNext_32$CLR,
sqrtfxm_sqrt_fNext_32$DEQ,
sqrtfxm_sqrt_fNext_32$EMPTY_N,
sqrtfxm_sqrt_fNext_32$ENQ,
sqrtfxm_sqrt_fNext_32$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_4
wire [256 : 0] sqrtfxm_sqrt_fNext_4$D_IN, sqrtfxm_sqrt_fNext_4$D_OUT;
wire sqrtfxm_sqrt_fNext_4$CLR,
sqrtfxm_sqrt_fNext_4$DEQ,
sqrtfxm_sqrt_fNext_4$EMPTY_N,
sqrtfxm_sqrt_fNext_4$ENQ,
sqrtfxm_sqrt_fNext_4$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_5
wire [256 : 0] sqrtfxm_sqrt_fNext_5$D_IN, sqrtfxm_sqrt_fNext_5$D_OUT;
wire sqrtfxm_sqrt_fNext_5$CLR,
sqrtfxm_sqrt_fNext_5$DEQ,
sqrtfxm_sqrt_fNext_5$EMPTY_N,
sqrtfxm_sqrt_fNext_5$ENQ,
sqrtfxm_sqrt_fNext_5$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_6
wire [256 : 0] sqrtfxm_sqrt_fNext_6$D_IN, sqrtfxm_sqrt_fNext_6$D_OUT;
wire sqrtfxm_sqrt_fNext_6$CLR,
sqrtfxm_sqrt_fNext_6$DEQ,
sqrtfxm_sqrt_fNext_6$EMPTY_N,
sqrtfxm_sqrt_fNext_6$ENQ,
sqrtfxm_sqrt_fNext_6$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_7
wire [256 : 0] sqrtfxm_sqrt_fNext_7$D_IN, sqrtfxm_sqrt_fNext_7$D_OUT;
wire sqrtfxm_sqrt_fNext_7$CLR,
sqrtfxm_sqrt_fNext_7$DEQ,
sqrtfxm_sqrt_fNext_7$EMPTY_N,
sqrtfxm_sqrt_fNext_7$ENQ,
sqrtfxm_sqrt_fNext_7$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_8
wire [256 : 0] sqrtfxm_sqrt_fNext_8$D_IN, sqrtfxm_sqrt_fNext_8$D_OUT;
wire sqrtfxm_sqrt_fNext_8$CLR,
sqrtfxm_sqrt_fNext_8$DEQ,
sqrtfxm_sqrt_fNext_8$EMPTY_N,
sqrtfxm_sqrt_fNext_8$ENQ,
sqrtfxm_sqrt_fNext_8$FULL_N;
// ports of submodule sqrtfxm_sqrt_fNext_9
wire [256 : 0] sqrtfxm_sqrt_fNext_9$D_IN, sqrtfxm_sqrt_fNext_9$D_OUT;
wire sqrtfxm_sqrt_fNext_9$CLR,
sqrtfxm_sqrt_fNext_9$DEQ,
sqrtfxm_sqrt_fNext_9$EMPTY_N,
sqrtfxm_sqrt_fNext_9$ENQ,
sqrtfxm_sqrt_fNext_9$FULL_N;
// ports of submodule sqrtfxm_sqrt_fRequest
wire [63 : 0] sqrtfxm_sqrt_fRequest$D_IN, sqrtfxm_sqrt_fRequest$D_OUT;
wire sqrtfxm_sqrt_fRequest$CLR,
sqrtfxm_sqrt_fRequest$DEQ,
sqrtfxm_sqrt_fRequest$EMPTY_N,
sqrtfxm_sqrt_fRequest$ENQ,
sqrtfxm_sqrt_fRequest$FULL_N;
// ports of submodule sqrtfxm_sqrt_fResponse
wire [64 : 0] sqrtfxm_sqrt_fResponse$D_IN, sqrtfxm_sqrt_fResponse$D_OUT;
wire sqrtfxm_sqrt_fResponse$CLR,
sqrtfxm_sqrt_fResponse$DEQ,
sqrtfxm_sqrt_fResponse$EMPTY_N,
sqrtfxm_sqrt_fResponse$ENQ,
sqrtfxm_sqrt_fResponse$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_sqrtfxm_finish,
CAN_FIRE_RL_sqrtfxm_sqrt_finish,
CAN_FIRE_RL_sqrtfxm_sqrt_start,
CAN_FIRE_RL_sqrtfxm_sqrt_work,
CAN_FIRE_RL_sqrtfxm_sqrt_work_1,
CAN_FIRE_RL_sqrtfxm_sqrt_work_10,
CAN_FIRE_RL_sqrtfxm_sqrt_work_11,
CAN_FIRE_RL_sqrtfxm_sqrt_work_12,
CAN_FIRE_RL_sqrtfxm_sqrt_work_13,
CAN_FIRE_RL_sqrtfxm_sqrt_work_14,
CAN_FIRE_RL_sqrtfxm_sqrt_work_15,
CAN_FIRE_RL_sqrtfxm_sqrt_work_16,
CAN_FIRE_RL_sqrtfxm_sqrt_work_17,
CAN_FIRE_RL_sqrtfxm_sqrt_work_18,
CAN_FIRE_RL_sqrtfxm_sqrt_work_19,
CAN_FIRE_RL_sqrtfxm_sqrt_work_2,
CAN_FIRE_RL_sqrtfxm_sqrt_work_20,
CAN_FIRE_RL_sqrtfxm_sqrt_work_21,
CAN_FIRE_RL_sqrtfxm_sqrt_work_22,
CAN_FIRE_RL_sqrtfxm_sqrt_work_23,
CAN_FIRE_RL_sqrtfxm_sqrt_work_24,
CAN_FIRE_RL_sqrtfxm_sqrt_work_25,
CAN_FIRE_RL_sqrtfxm_sqrt_work_26,
CAN_FIRE_RL_sqrtfxm_sqrt_work_27,
CAN_FIRE_RL_sqrtfxm_sqrt_work_28,
CAN_FIRE_RL_sqrtfxm_sqrt_work_29,
CAN_FIRE_RL_sqrtfxm_sqrt_work_3,
CAN_FIRE_RL_sqrtfxm_sqrt_work_30,
CAN_FIRE_RL_sqrtfxm_sqrt_work_31,
CAN_FIRE_RL_sqrtfxm_sqrt_work_32,
CAN_FIRE_RL_sqrtfxm_sqrt_work_4,
CAN_FIRE_RL_sqrtfxm_sqrt_work_5,
CAN_FIRE_RL_sqrtfxm_sqrt_work_6,
CAN_FIRE_RL_sqrtfxm_sqrt_work_7,
CAN_FIRE_RL_sqrtfxm_sqrt_work_8,
CAN_FIRE_RL_sqrtfxm_sqrt_work_9,
CAN_FIRE_RL_sqrtfxm_start,
CAN_FIRE_RL_testFSM_action_l75c16,
CAN_FIRE_RL_testFSM_action_l76c16,
CAN_FIRE_RL_testFSM_fsm_start,
CAN_FIRE_RL_testFSM_idle_l74c5,
CAN_FIRE_RL_testFSM_restart,
CAN_FIRE_RL_testFSM_start_reg__dreg_update,
CAN_FIRE_RL_testFSM_state_every,
CAN_FIRE_RL_testFSM_state_fired__dreg_update,
CAN_FIRE_RL_testFSM_state_handle_abort,
CAN_FIRE___me_check_42,
CAN_FIRE_get,
CAN_FIRE_initialize,
CAN_FIRE_run,
WILL_FIRE_RL_sqrtfxm_finish,
WILL_FIRE_RL_sqrtfxm_sqrt_finish,
WILL_FIRE_RL_sqrtfxm_sqrt_start,
WILL_FIRE_RL_sqrtfxm_sqrt_work,
WILL_FIRE_RL_sqrtfxm_sqrt_work_1,
WILL_FIRE_RL_sqrtfxm_sqrt_work_10,
WILL_FIRE_RL_sqrtfxm_sqrt_work_11,
WILL_FIRE_RL_sqrtfxm_sqrt_work_12,
WILL_FIRE_RL_sqrtfxm_sqrt_work_13,
WILL_FIRE_RL_sqrtfxm_sqrt_work_14,
WILL_FIRE_RL_sqrtfxm_sqrt_work_15,
WILL_FIRE_RL_sqrtfxm_sqrt_work_16,
WILL_FIRE_RL_sqrtfxm_sqrt_work_17,
WILL_FIRE_RL_sqrtfxm_sqrt_work_18,
WILL_FIRE_RL_sqrtfxm_sqrt_work_19,
WILL_FIRE_RL_sqrtfxm_sqrt_work_2,
WILL_FIRE_RL_sqrtfxm_sqrt_work_20,
WILL_FIRE_RL_sqrtfxm_sqrt_work_21,
WILL_FIRE_RL_sqrtfxm_sqrt_work_22,
WILL_FIRE_RL_sqrtfxm_sqrt_work_23,
WILL_FIRE_RL_sqrtfxm_sqrt_work_24,
WILL_FIRE_RL_sqrtfxm_sqrt_work_25,
WILL_FIRE_RL_sqrtfxm_sqrt_work_26,
WILL_FIRE_RL_sqrtfxm_sqrt_work_27,
WILL_FIRE_RL_sqrtfxm_sqrt_work_28,
WILL_FIRE_RL_sqrtfxm_sqrt_work_29,
WILL_FIRE_RL_sqrtfxm_sqrt_work_3,
WILL_FIRE_RL_sqrtfxm_sqrt_work_30,
WILL_FIRE_RL_sqrtfxm_sqrt_work_31,
WILL_FIRE_RL_sqrtfxm_sqrt_work_32,
WILL_FIRE_RL_sqrtfxm_sqrt_work_4,
WILL_FIRE_RL_sqrtfxm_sqrt_work_5,
WILL_FIRE_RL_sqrtfxm_sqrt_work_6,
WILL_FIRE_RL_sqrtfxm_sqrt_work_7,
WILL_FIRE_RL_sqrtfxm_sqrt_work_8,
WILL_FIRE_RL_sqrtfxm_sqrt_work_9,
WILL_FIRE_RL_sqrtfxm_start,
WILL_FIRE_RL_testFSM_action_l75c16,
WILL_FIRE_RL_testFSM_action_l76c16,
WILL_FIRE_RL_testFSM_fsm_start,
WILL_FIRE_RL_testFSM_idle_l74c5,
WILL_FIRE_RL_testFSM_restart,
WILL_FIRE_RL_testFSM_start_reg__dreg_update,
WILL_FIRE_RL_testFSM_state_every,
WILL_FIRE_RL_testFSM_state_fired__dreg_update,
WILL_FIRE_RL_testFSM_state_handle_abort,
WILL_FIRE___me_check_42,
WILL_FIRE_get,
WILL_FIRE_initialize,
WILL_FIRE_run;
// inputs to muxes for submodule ports
wire MUX_testFSM_start_reg$write_1__SEL_1;
// remaining internal signals
wire [191 : 0] IF_sqrtfxm_sqrt_fFirst_first__44_BIT_256_45_TH_ETC___d174,
IF_sqrtfxm_sqrt_fNext_0_first__79_BIT_256_80_T_ETC___d209,
IF_sqrtfxm_sqrt_fNext_10_first__29_BIT_256_30__ETC___d559,
IF_sqrtfxm_sqrt_fNext_11_first__64_BIT_256_65__ETC___d594,
IF_sqrtfxm_sqrt_fNext_12_first__99_BIT_256_00__ETC___d629,
IF_sqrtfxm_sqrt_fNext_13_first__34_BIT_256_35__ETC___d664,
IF_sqrtfxm_sqrt_fNext_14_first__69_BIT_256_70__ETC___d699,
IF_sqrtfxm_sqrt_fNext_15_first__04_BIT_256_05__ETC___d734,
IF_sqrtfxm_sqrt_fNext_16_first__39_BIT_256_40__ETC___d769,
IF_sqrtfxm_sqrt_fNext_17_first__74_BIT_256_75__ETC___d804,
IF_sqrtfxm_sqrt_fNext_18_first__09_BIT_256_10__ETC___d839,
IF_sqrtfxm_sqrt_fNext_19_first__44_BIT_256_45__ETC___d874,
IF_sqrtfxm_sqrt_fNext_1_first__14_BIT_256_15_T_ETC___d244,
IF_sqrtfxm_sqrt_fNext_20_first__79_BIT_256_80__ETC___d909,
IF_sqrtfxm_sqrt_fNext_21_first__14_BIT_256_15__ETC___d944,
IF_sqrtfxm_sqrt_fNext_22_first__49_BIT_256_50__ETC___d979,
IF_sqrtfxm_sqrt_fNext_23_first__84_BIT_256_85__ETC___d1014,
IF_sqrtfxm_sqrt_fNext_24_first__019_BIT_256_02_ETC___d1049,
IF_sqrtfxm_sqrt_fNext_25_first__054_BIT_256_05_ETC___d1084,
IF_sqrtfxm_sqrt_fNext_26_first__089_BIT_256_09_ETC___d1119,
IF_sqrtfxm_sqrt_fNext_27_first__124_BIT_256_12_ETC___d1154,
IF_sqrtfxm_sqrt_fNext_28_first__159_BIT_256_16_ETC___d1189,
IF_sqrtfxm_sqrt_fNext_29_first__194_BIT_256_19_ETC___d1224,
IF_sqrtfxm_sqrt_fNext_2_first__49_BIT_256_50_T_ETC___d279,
IF_sqrtfxm_sqrt_fNext_30_first__229_BIT_256_23_ETC___d1259,
IF_sqrtfxm_sqrt_fNext_31_first__264_BIT_256_26_ETC___d1294,
IF_sqrtfxm_sqrt_fNext_3_first__84_BIT_256_85_T_ETC___d314,
IF_sqrtfxm_sqrt_fNext_4_first__19_BIT_256_20_T_ETC___d349,
IF_sqrtfxm_sqrt_fNext_5_first__54_BIT_256_55_T_ETC___d384,
IF_sqrtfxm_sqrt_fNext_6_first__89_BIT_256_90_T_ETC___d419,
IF_sqrtfxm_sqrt_fNext_7_first__24_BIT_256_25_T_ETC___d454,
IF_sqrtfxm_sqrt_fNext_8_first__59_BIT_256_60_T_ETC___d489,
IF_sqrtfxm_sqrt_fNext_9_first__94_BIT_256_95_T_ETC___d524;
wire [129 : 0] IF_r1_523_BIT_64_524_THEN_NEG_0_CONCAT_IF_r1_5_ETC___d1529,
IF_r2_563_BIT_64_564_THEN_NEG_0_CONCAT_IF_r2_5_ETC___d1569,
_0_CONCAT_IF_r1_523_BIT_64_524_THEN_NEG_r1_523__ETC___d1527,
_0_CONCAT_IF_r2_563_BIT_64_564_THEN_NEG_r2_563__ETC___d1567,
x__h84762,
x__h91164;
wire [97 : 0] IF_IF_NOT_IF_NOT_IF_r1_523_BIT_64_524_THEN_NEG_ETC___d1618,
IF_IF_NOT_IF_NOT_IF_r2_563_BIT_64_564_THEN_NEG_ETC___d1654,
IF_NOT_IF_r1_523_BIT_64_524_THEN_NEG_0_CONCAT__ETC___d1544,
IF_NOT_IF_r2_563_BIT_64_564_THEN_NEG_0_CONCAT__ETC___d1584,
IF_r1_523_BIT_64_524_THEN_NEG_0_CONCAT_IF_r1_5_ETC___d1541,
IF_r2_563_BIT_64_564_THEN_NEG_0_CONCAT_IF_r2_5_ETC___d1581,
x__h83993,
x__h90395;
wire [64 : 0] IF_NOT_IF_NOT_IF_r1_523_BIT_64_524_THEN_NEG_0__ETC___d1562,
IF_NOT_IF_NOT_IF_r2_563_BIT_64_564_THEN_NEG_0__ETC___d1602,
x__h84807,
x__h91209;
wire [63 : 0] _theResult___fst__h23637,
_theResult___fst__h24067,
_theResult___fst__h24495,
_theResult___fst__h24923,
_theResult___fst__h25351,
_theResult___fst__h25779,
_theResult___fst__h26207,
_theResult___fst__h26635,
_theResult___fst__h27063,
_theResult___fst__h27491,
_theResult___fst__h27919,
_theResult___fst__h28347,
_theResult___fst__h28775,
_theResult___fst__h29203,
_theResult___fst__h29631,
_theResult___fst__h30059,
_theResult___fst__h30487,
_theResult___fst__h30915,
_theResult___fst__h31343,
_theResult___fst__h31771,
_theResult___fst__h32199,
_theResult___fst__h32627,
_theResult___fst__h33055,
_theResult___fst__h33483,
_theResult___fst__h33911,
_theResult___fst__h34339,
_theResult___fst__h34767,
_theResult___fst__h35195,
_theResult___fst__h35623,
_theResult___fst__h36051,
_theResult___fst__h36479,
_theResult___fst__h36907,
_theResult___fst__h37335,
_theResult___snd_snd__h23729,
_theResult___snd_snd__h24157,
_theResult___snd_snd__h24585,
_theResult___snd_snd__h25013,
_theResult___snd_snd__h25441,
_theResult___snd_snd__h25869,
_theResult___snd_snd__h26297,
_theResult___snd_snd__h26725,
_theResult___snd_snd__h27153,
_theResult___snd_snd__h27581,
_theResult___snd_snd__h28009,
_theResult___snd_snd__h28437,
_theResult___snd_snd__h28865,
_theResult___snd_snd__h29293,
_theResult___snd_snd__h29721,
_theResult___snd_snd__h30149,
_theResult___snd_snd__h30577,
_theResult___snd_snd__h31005,
_theResult___snd_snd__h31433,
_theResult___snd_snd__h31861,
_theResult___snd_snd__h32289,
_theResult___snd_snd__h32717,
_theResult___snd_snd__h33145,
_theResult___snd_snd__h33573,
_theResult___snd_snd__h34001,
_theResult___snd_snd__h34429,
_theResult___snd_snd__h34857,
_theResult___snd_snd__h35285,
_theResult___snd_snd__h35713,
_theResult___snd_snd__h36141,
_theResult___snd_snd__h36569,
_theResult___snd_snd__h36997,
_theResult___snd_snd__h37425,
b___1__h11623,
b__h23715,
b__h24143,
b__h24571,
b__h24999,
b__h25427,
b__h25855,
b__h26283,
b__h26711,
b__h27139,
b__h27567,
b__h27995,
b__h28423,
b__h28851,
b__h29279,
b__h29707,
b__h30135,
b__h30563,
b__h30991,
b__h31419,
b__h31847,
b__h32275,
b__h32703,
b__h33131,
b__h33559,
b__h33987,
b__h34415,
b__h34843,
b__h35271,
b__h35699,
b__h36127,
b__h36555,
b__h36983,
b__h37411,
b__h37581,
r__h23726,
r__h23741,
r__h24154,
r__h24169,
r__h24582,
r__h24597,
r__h25010,
r__h25025,
r__h25438,
r__h25453,
r__h25866,
r__h25881,
r__h26294,
r__h26309,
r__h26722,
r__h26737,
r__h27150,
r__h27165,
r__h27578,
r__h27593,
r__h28006,
r__h28021,
r__h28434,
r__h28449,
r__h28862,
r__h28877,
r__h29290,
r__h29305,
r__h29718,
r__h29733,
r__h30146,
r__h30161,
r__h30574,
r__h30589,
r__h31002,
r__h31017,
r__h31430,
r__h31445,
r__h31858,
r__h31873,
r__h32286,
r__h32301,
r__h32714,
r__h32729,
r__h33142,
r__h33157,
r__h33570,
r__h33585,
r__h33998,
r__h34013,
r__h34426,
r__h34441,
r__h34854,
r__h34869,
r__h35282,
r__h35297,
r__h35710,
r__h35725,
r__h36138,
r__h36153,
r__h36566,
r__h36581,
r__h36994,
r__h37009,
r__h37422,
r__h37437,
s__h23725,
s__h24153,
s__h24581,
s__h25009,
s__h25437,
s__h25865,
s__h26293,
s__h26721,
s__h27149,
s__h27577,
s__h28005,
s__h28433,
s__h28861,
s__h29289,
s__h29717,
s__h30145,
s__h30573,
s__h31001,
s__h31429,
s__h31857,
s__h32285,
s__h32713,
s__h33141,
s__h33569,
s__h33997,
s__h34425,
s__h34853,
s__h35281,
s__h35709,
s__h36137,
s__h36565,
s__h36993,
s__h37421,
sum__h23713,
sum__h24141,
sum__h24569,
sum__h24997,
sum__h25425,
sum__h25853,
sum__h26281,
sum__h26709,
sum__h27137,
sum__h27565,
sum__h27993,
sum__h28421,
sum__h28849,
sum__h29277,
sum__h29705,
sum__h30133,
sum__h30561,
sum__h30989,
sum__h31417,
sum__h31845,
sum__h32273,
sum__h32701,
sum__h33129,
sum__h33557,
sum__h33985,
sum__h34413,
sum__h34841,
sum__h35269,
sum__h35697,
sum__h36125,
sum__h36553,
sum__h36981,
sum__h37409,
x__h48695,
x__h961;
wire [31 : 0] y_f__h73719, y_f__h80302, y_f__h86830, y_f__h93232;
wire [6 : 0] IF_sqrtfxm_fRequestD_OUT_BIT_63_THEN_0_ELSE_I_ETC__q1,
IF_sqrtfxm_sqrt_fRequest_first_BIT_63_THEN_0_E_ETC___d133,
x8534_PLUS_32__q2,
x__h23327,
x__h48534,
x__h48778;
wire sqrtfxm_sqrt_fFirst_first__44_BITS_191_TO_128__ETC___d160,
sqrtfxm_sqrt_fNext_0_first__79_BITS_191_TO_128_ETC___d195,
sqrtfxm_sqrt_fNext_10_first__29_BITS_191_TO_12_ETC___d545,
sqrtfxm_sqrt_fNext_11_first__64_BITS_191_TO_12_ETC___d580,
sqrtfxm_sqrt_fNext_12_first__99_BITS_191_TO_12_ETC___d615,
sqrtfxm_sqrt_fNext_13_first__34_BITS_191_TO_12_ETC___d650,
sqrtfxm_sqrt_fNext_14_first__69_BITS_191_TO_12_ETC___d685,
sqrtfxm_sqrt_fNext_15_first__04_BITS_191_TO_12_ETC___d720,
sqrtfxm_sqrt_fNext_16_first__39_BITS_191_TO_12_ETC___d755,
sqrtfxm_sqrt_fNext_17_first__74_BITS_191_TO_12_ETC___d790,
sqrtfxm_sqrt_fNext_18_first__09_BITS_191_TO_12_ETC___d825,
sqrtfxm_sqrt_fNext_19_first__44_BITS_191_TO_12_ETC___d860,
sqrtfxm_sqrt_fNext_1_first__14_BITS_191_TO_128_ETC___d230,
sqrtfxm_sqrt_fNext_20_first__79_BITS_191_TO_12_ETC___d895,
sqrtfxm_sqrt_fNext_21_first__14_BITS_191_TO_12_ETC___d930,
sqrtfxm_sqrt_fNext_22_first__49_BITS_191_TO_12_ETC___d965,
sqrtfxm_sqrt_fNext_23_first__84_BITS_191_TO_12_ETC___d1000,
sqrtfxm_sqrt_fNext_24_first__019_BITS_191_TO_1_ETC___d1035,
sqrtfxm_sqrt_fNext_25_first__054_BITS_191_TO_1_ETC___d1070,
sqrtfxm_sqrt_fNext_26_first__089_BITS_191_TO_1_ETC___d1105,
sqrtfxm_sqrt_fNext_27_first__124_BITS_191_TO_1_ETC___d1140,
sqrtfxm_sqrt_fNext_28_first__159_BITS_191_TO_1_ETC___d1175,
sqrtfxm_sqrt_fNext_29_first__194_BITS_191_TO_1_ETC___d1210,
sqrtfxm_sqrt_fNext_2_first__49_BITS_191_TO_128_ETC___d265,
sqrtfxm_sqrt_fNext_30_first__229_BITS_191_TO_1_ETC___d1245,
sqrtfxm_sqrt_fNext_31_first__264_BITS_191_TO_1_ETC___d1280,
sqrtfxm_sqrt_fNext_3_first__84_BITS_191_TO_128_ETC___d300,
sqrtfxm_sqrt_fNext_4_first__19_BITS_191_TO_128_ETC___d335,
sqrtfxm_sqrt_fNext_5_first__54_BITS_191_TO_128_ETC___d370,
sqrtfxm_sqrt_fNext_6_first__89_BITS_191_TO_128_ETC___d405,
sqrtfxm_sqrt_fNext_7_first__24_BITS_191_TO_128_ETC___d440,
sqrtfxm_sqrt_fNext_8_first__59_BITS_191_TO_128_ETC___d475,
sqrtfxm_sqrt_fNext_9_first__94_BITS_191_TO_128_ETC___d510,
testFSM_abort_whas__468_AND_testFSM_abort_wget_ETC___d1514;
// action method initialize
assign RDY_initialize = 1'd1 ;
assign CAN_FIRE_initialize = 1'd1 ;
assign WILL_FIRE_initialize = EN_initialize ;
// action method run
assign RDY_run =
testFSM_abort_whas__468_AND_testFSM_abort_wget_ETC___d1514 &&
!testFSM_start_reg ;
assign CAN_FIRE_run =
testFSM_abort_whas__468_AND_testFSM_abort_wget_ETC___d1514 &&
!testFSM_start_reg ;
assign WILL_FIRE_run = EN_run ;
// actionvalue method get
assign get = { v1, v2, valsqrOut, valsqrOut } ;
assign RDY_get = 1'd1 ;
assign CAN_FIRE_get = 1'd1 ;
assign WILL_FIRE_get = EN_get ;
// submodule fCheck
FIFOL1 #(.width(32'd64)) fCheck(.RST(RST_N),
.CLK(CLK),
.D_IN(fCheck$D_IN),
.ENQ(fCheck$ENQ),
.DEQ(fCheck$DEQ),
.CLR(fCheck$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule mLUT
mkLogTableFxdP mLUT(.CLK(CLK),
.RST_N(RST_N),
.run_input_val(mLUT$run_input_val),
.EN_run(mLUT$EN_run),
.EN_get(mLUT$EN_get),
.RDY_run(),
.get(),
.RDY_get());
// submodule rgn1
mkWellPRNG rgn1(.CLK(CLK),
.RST_N(RST_N),
.initialize_s(rgn1$initialize_s),
.EN_initialize(rgn1$EN_initialize),
.EN_get(rgn1$EN_get),
.RDY_initialize(),
.get(rgn1$get),
.RDY_get());
// submodule rgn2
mkWellPRNG rgn2(.CLK(CLK),
.RST_N(RST_N),
.initialize_s(rgn2$initialize_s),
.EN_initialize(rgn2$EN_initialize),
.EN_get(rgn2$EN_get),
.RDY_initialize(),
.get(rgn2$get),
.RDY_get());
// submodule sqrtfxm_fRequest
FIFOL1 #(.width(32'd64)) sqrtfxm_fRequest(.RST(RST_N),
.CLK(CLK),
.D_IN(sqrtfxm_fRequest$D_IN),
.ENQ(sqrtfxm_fRequest$ENQ),
.DEQ(sqrtfxm_fRequest$DEQ),
.CLR(sqrtfxm_fRequest$CLR),
.D_OUT(sqrtfxm_fRequest$D_OUT),
.FULL_N(sqrtfxm_fRequest$FULL_N),
.EMPTY_N(sqrtfxm_fRequest$EMPTY_N));
// submodule sqrtfxm_fResponse
FIFOL1 #(.width(32'd65)) sqrtfxm_fResponse(.RST(RST_N),
.CLK(CLK),
.D_IN(sqrtfxm_fResponse$D_IN),
.ENQ(sqrtfxm_fResponse$ENQ),
.DEQ(sqrtfxm_fResponse$DEQ),
.CLR(sqrtfxm_fResponse$CLR),
.D_OUT(sqrtfxm_fResponse$D_OUT),
.FULL_N(sqrtfxm_fResponse$FULL_N),
.EMPTY_N(sqrtfxm_fResponse$EMPTY_N));
// submodule sqrtfxm_fShift