mkWellPRNG.v

//
// Generated by Bluespec Compiler, version 2014.07.A (build 34078, 2014-07-30)
//
// On Wed Jul  4 22:01:56 -03 2018
//
//
// Ports:
// Name                         I/O  size props
// RDY_initialize                 O     1 const
// get                            O    32
// RDY_get                        O     1 const
// CLK                            I     1 clock
// RST_N                          I     1 unused
// initialize_s                   I    32
// EN_initialize                  I     1
// EN_get                         I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkWellPRNG(CLK,
		  RST_N,

		  initialize_s,
		  EN_initialize,
		  RDY_initialize,

		  EN_get,
		  get,
		  RDY_get);
  input  CLK;
  input  RST_N;

  // action method initialize
  input  [31 : 0] initialize_s;
  input  EN_initialize;
  output RDY_initialize;

  // actionvalue method get
  input  EN_get;
  output [31 : 0] get;
  output RDY_get;

  // signals for module outputs
  reg [31 : 0] get;
  wire RDY_get, RDY_initialize;

  // register state_0
  reg [31 : 0] state_0;
  wire [31 : 0] state_0$D_IN;
  wire state_0$EN;

  // register state_1
  reg [31 : 0] state_1;
  wire [31 : 0] state_1$D_IN;
  wire state_1$EN;

  // register state_10
  reg [31 : 0] state_10;
  wire [31 : 0] state_10$D_IN;
  wire state_10$EN;

  // register state_11
  reg [31 : 0] state_11;
  wire [31 : 0] state_11$D_IN;
  wire state_11$EN;

  // register state_12
  reg [31 : 0] state_12;
  wire [31 : 0] state_12$D_IN;
  wire state_12$EN;

  // register state_13
  reg [31 : 0] state_13;
  wire [31 : 0] state_13$D_IN;
  wire state_13$EN;

  // register state_14
  reg [31 : 0] state_14;
  wire [31 : 0] state_14$D_IN;
  wire state_14$EN;

  // register state_15
  reg [31 : 0] state_15;
  wire [31 : 0] state_15$D_IN;
  wire state_15$EN;

  // register state_2
  reg [31 : 0] state_2;
  wire [31 : 0] state_2$D_IN;
  wire state_2$EN;

  // register state_3
  reg [31 : 0] state_3;
  wire [31 : 0] state_3$D_IN;
  wire state_3$EN;

  // register state_4
  reg [31 : 0] state_4;
  wire [31 : 0] state_4$D_IN;
  wire state_4$EN;

  // register state_5
  reg [31 : 0] state_5;
  wire [31 : 0] state_5$D_IN;
  wire state_5$EN;

  // register state_6
  reg [31 : 0] state_6;
  wire [31 : 0] state_6$D_IN;
  wire state_6$EN;

  // register state_7
  reg [31 : 0] state_7;
  wire [31 : 0] state_7$D_IN;
  wire state_7$EN;

  // register state_8
  reg [31 : 0] state_8;
  wire [31 : 0] state_8$D_IN;
  wire state_8$EN;

  // register state_9
  reg [31 : 0] state_9;
  wire [31 : 0] state_9$D_IN;
  wire state_9$EN;

  // register state_i
  reg [31 : 0] state_i;
  wire [31 : 0] state_i$D_IN;
  wire state_i$EN;

  // register z0
  reg [31 : 0] z0;
  wire [31 : 0] z0$D_IN;
  wire z0$EN;

  // register z1
  reg [31 : 0] z1;
  wire [31 : 0] z1$D_IN;
  wire z1$EN;

  // register z2
  reg [31 : 0] z2;
  wire [31 : 0] z2$D_IN;
  wire z2$EN;

  // rule scheduling signals
  wire CAN_FIRE_get, CAN_FIRE_initialize, WILL_FIRE_get, WILL_FIRE_initialize;

  // inputs to muxes for submodule ports
  wire [31 : 0] MUX_state_0$write_1__VAL_1,
		MUX_state_0$write_1__VAL_2,
		MUX_state_1$write_1__VAL_1,
		MUX_state_1$write_1__VAL_2,
		MUX_state_10$write_1__VAL_2,
		MUX_state_11$write_1__VAL_2,
		MUX_state_12$write_1__VAL_2,
		MUX_state_13$write_1__VAL_2,
		MUX_state_14$write_1__VAL_2,
		MUX_state_15$write_1__VAL_2,
		MUX_state_2$write_1__VAL_1,
		MUX_state_2$write_1__VAL_2,
		MUX_state_3$write_1__VAL_2,
		MUX_state_4$write_1__VAL_2,
		MUX_state_5$write_1__VAL_2,
		MUX_state_6$write_1__VAL_2,
		MUX_state_7$write_1__VAL_2,
		MUX_state_8$write_1__VAL_2,
		MUX_state_9$write_1__VAL_2;

  // remaining internal signals
  reg [31 : 0] v__h3191, v__h3268, z0__h2532;
  wire [31 : 0] n__h3871,
		n__h3875,
		state_i_PLUS_13__q1,
		state_i_PLUS_15__q2,
		state_i_PLUS_9__q3,
		v__h3137,
		x__h2569,
		x__h3134,
		x__h3205,
		x__h3283,
		x__h3909,
		x__h3911,
		x__h3913,
		y__h3135,
		y__h3150,
		y__h3204,
		y__h3281,
		y__h3910,
		y__h3912,
		y__h3914,
		y__h3928,
		y__h3955,
		y__h4000,
		z1__h2533,
		z2__h2534;

  // action method initialize
  assign RDY_initialize = 1'd1 ;
  assign CAN_FIRE_initialize = 1'd1 ;
  assign WILL_FIRE_initialize = EN_initialize ;

  // actionvalue method get
  always@(state_i or
	  state_0 or
	  state_1 or
	  state_2 or
	  state_3 or
	  state_4 or
	  state_5 or
	  state_6 or
	  state_7 or
	  state_8 or
	  state_9 or
	  state_10 or
	  state_11 or state_12 or state_13 or state_14 or state_15)
  begin
    case (state_i)
      32'd0: get = state_0;
      32'd1: get = state_1;
      32'd2: get = state_2;
      32'd3: get = state_3;
      32'd4: get = state_4;
      32'd5: get = state_5;
      32'd6: get = state_6;
      32'd7: get = state_7;
      32'd8: get = state_8;
      32'd9: get = state_9;
      32'd10: get = state_10;
      32'd11: get = state_11;
      32'd12: get = state_12;
      32'd13: get = state_13;
      32'd14: get = state_14;
      32'd15: get = state_15;
      default: get = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign RDY_get = 1'd1 ;
  assign CAN_FIRE_get = 1'd1 ;
  assign WILL_FIRE_get = EN_get ;

  // inputs to muxes for submodule ports
  assign MUX_state_0$write_1__VAL_1 = initialize_s + 32'd72852922 ;
  assign MUX_state_0$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd0) ?
	       n__h3871 :
	       ((state_i == 32'd0) ? n__h3875 : state_0) ;
  assign MUX_state_1$write_1__VAL_1 = initialize_s + 32'd41699578 ;
  assign MUX_state_1$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd1) ?
	       n__h3871 :
	       ((state_i == 32'd1) ? n__h3875 : state_1) ;
  assign MUX_state_10$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd10) ?
	       n__h3871 :
	       ((state_i == 32'd10) ? n__h3875 : state_10) ;
  assign MUX_state_11$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd11) ?
	       n__h3871 :
	       ((state_i == 32'd11) ? n__h3875 : state_11) ;
  assign MUX_state_12$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd12) ?
	       n__h3871 :
	       ((state_i == 32'd12) ? n__h3875 : state_12) ;
  assign MUX_state_13$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd13) ?
	       n__h3871 :
	       ((state_i == 32'd13) ? n__h3875 : state_13) ;
  assign MUX_state_14$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd14) ?
	       n__h3871 :
	       ((state_i == 32'd14) ? n__h3875 : state_14) ;
  assign MUX_state_15$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd15) ?
	       n__h3871 :
	       ((state_i == 32'd15) ? n__h3875 : state_15) ;
  assign MUX_state_2$write_1__VAL_1 = initialize_s + 32'd56707026 ;
  assign MUX_state_2$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd2) ?
	       n__h3871 :
	       ((state_i == 32'd2) ? n__h3875 : state_2) ;
  assign MUX_state_3$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd3) ?
	       n__h3871 :
	       ((state_i == 32'd3) ? n__h3875 : state_3) ;
  assign MUX_state_4$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd4) ?
	       n__h3871 :
	       ((state_i == 32'd4) ? n__h3875 : state_4) ;
  assign MUX_state_5$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd5) ?
	       n__h3871 :
	       ((state_i == 32'd5) ? n__h3875 : state_5) ;
  assign MUX_state_6$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd6) ?
	       n__h3871 :
	       ((state_i == 32'd6) ? n__h3875 : state_6) ;
  assign MUX_state_7$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd7) ?
	       n__h3871 :
	       ((state_i == 32'd7) ? n__h3875 : state_7) ;
  assign MUX_state_8$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd8) ?
	       n__h3871 :
	       ((state_i == 32'd8) ? n__h3875 : state_8) ;
  assign MUX_state_9$write_1__VAL_2 =
	     (state_i_PLUS_15__q2[3:0] == 4'd9) ?
	       n__h3871 :
	       ((state_i == 32'd9) ? n__h3875 : state_9) ;

  // register state_0
  assign state_0$D_IN =
	     EN_initialize ?
	       MUX_state_0$write_1__VAL_1 :
	       MUX_state_0$write_1__VAL_2 ;
  assign state_0$EN = EN_initialize || EN_get ;

  // register state_1
  assign state_1$D_IN =
	     EN_initialize ?
	       MUX_state_1$write_1__VAL_1 :
	       MUX_state_1$write_1__VAL_2 ;
  assign state_1$EN = EN_initialize || EN_get ;

  // register state_10
  assign state_10$D_IN =
	     EN_initialize ? 32'd57870066 : MUX_state_10$write_1__VAL_2 ;
  assign state_10$EN = EN_get || EN_initialize ;

  // register state_11
  assign state_11$D_IN =
	     EN_initialize ? 32'd37220400 : MUX_state_11$write_1__VAL_2 ;
  assign state_11$EN = EN_get || EN_initialize ;

  // register state_12
  assign state_12$D_IN =
	     EN_initialize ? 32'd14597146 : MUX_state_12$write_1__VAL_2 ;
  assign state_12$EN = EN_get || EN_initialize ;

  // register state_13
  assign state_13$D_IN =
	     EN_initialize ? 32'd1165159 : MUX_state_13$write_1__VAL_2 ;
  assign state_13$EN = EN_get || EN_initialize ;

  // register state_14
  assign state_14$D_IN =
	     EN_initialize ? 32'd99349121 : MUX_state_14$write_1__VAL_2 ;
  assign state_14$EN = EN_get || EN_initialize ;

  // register state_15
  assign state_15$D_IN =
	     EN_initialize ? 32'd68083911 : MUX_state_15$write_1__VAL_2 ;
  assign state_15$EN = EN_get || EN_initialize ;

  // register state_2
  assign state_2$D_IN =
	     EN_initialize ?
	       MUX_state_2$write_1__VAL_1 :
	       MUX_state_2$write_1__VAL_2 ;
  assign state_2$EN = EN_initialize || EN_get ;

  // register state_3
  assign state_3$D_IN =
	     EN_initialize ? 32'd33717249 : MUX_state_3$write_1__VAL_2 ;
  assign state_3$EN = EN_get || EN_initialize ;

  // register state_4
  assign state_4$D_IN =
	     EN_initialize ? 32'd18306974 : MUX_state_4$write_1__VAL_2 ;
  assign state_4$EN = EN_get || EN_initialize ;

  // register state_5
  assign state_5$D_IN =
	     EN_initialize ? 32'd30824004 : MUX_state_5$write_1__VAL_2 ;
  assign state_5$EN = EN_get || EN_initialize ;

  // register state_6
  assign state_6$D_IN =
	     EN_initialize ? 32'd42901955 : MUX_state_6$write_1__VAL_2 ;
  assign state_6$EN = EN_get || EN_initialize ;

  // register state_7
  assign state_7$D_IN =
	     EN_initialize ? 32'd80465302 : MUX_state_7$write_1__VAL_2 ;
  assign state_7$EN = EN_get || EN_initialize ;

  // register state_8
  assign state_8$D_IN =
	     EN_initialize ? 32'd94968136 : MUX_state_8$write_1__VAL_2 ;
  assign state_8$EN = EN_get || EN_initialize ;

  // register state_9
  assign state_9$D_IN =
	     EN_initialize ? 32'd41480876 : MUX_state_9$write_1__VAL_2 ;
  assign state_9$EN = EN_get || EN_initialize ;

  // register state_i
  assign state_i$D_IN = x__h2569 ;
  assign state_i$EN = EN_get ;

  // register z0
  assign z0$D_IN = z0__h2532 ;
  assign z0$EN = EN_get ;

  // register z1
  assign z1$D_IN = z1__h2533 ;
  assign z1$EN = EN_get ;

  // register z2
  assign z2$D_IN = z2__h2534 ;
  assign z2$EN = EN_get ;

  // remaining internal signals
  assign n__h3871 = x__h3909 ^ y__h3910 ;
  assign n__h3875 = z1__h2533 ^ z2__h2534 ;
  assign state_i_PLUS_13__q1 = state_i + 32'd13 ;
  assign state_i_PLUS_15__q2 = state_i + 32'd15 ;
  assign state_i_PLUS_9__q3 = state_i + 32'd9 ;
  assign v__h3137 = get ;
  assign x__h2569 = { 28'd0, state_i_PLUS_15__q2[3:0] } ;
  assign x__h3134 = v__h3137 ^ y__h3150 ;
  assign x__h3205 = { 28'd0, state_i_PLUS_13__q1[3:0] } ;
  assign x__h3283 = { 28'd0, state_i_PLUS_9__q3[3:0] } ;
  assign x__h3909 = x__h3911 ^ y__h3912 ;
  assign x__h3911 = x__h3913 ^ y__h3914 ;
  assign x__h3913 = z0__h2532 ^ y__h3928 ;
  assign y__h3135 = v__h3191 ^ y__h3204 ;
  assign y__h3150 = { v__h3137[15:0], 16'd0 } ;
  assign y__h3204 = { v__h3191[16:0], 15'd0 } ;
  assign y__h3281 = { 11'd0, v__h3268[31:11] } ;
  assign y__h3910 = n__h3875 ^ y__h4000 ;
  assign y__h3912 = { z2__h2534[3:0], 28'd0 } ;
  assign y__h3914 = z1__h2533 ^ y__h3955 ;
  assign y__h3928 = { z0__h2532[29:0], 2'd0 } ;
  assign y__h3955 = { z1__h2533[13:0], 18'd0 } ;
  assign y__h4000 =
	     { n__h3875[26:25],
	       1'd0,
	       n__h3875[23:22],
	       1'd0,
	       n__h3875[20],
	       2'd0,
	       n__h3875[17],
	       3'd0,
	       n__h3875[13],
	       4'd0,
	       n__h3875[8],
	       1'd0,
	       n__h3875[6:5],
	       1'd0,
	       n__h3875[3],
	       2'd0,
	       n__h3875[0],
	       5'd0 } ;
  assign z1__h2533 = x__h3134 ^ y__h3135 ;
  assign z2__h2534 = v__h3268 ^ y__h3281 ;
  always@(x__h3205 or
	  state_0 or
	  state_1 or
	  state_2 or
	  state_3 or
	  state_4 or
	  state_5 or
	  state_6 or
	  state_7 or
	  state_8 or
	  state_9 or
	  state_10 or
	  state_11 or state_12 or state_13 or state_14 or state_15)
  begin
    case (x__h3205)
      32'd0: v__h3191 = state_0;
      32'd1: v__h3191 = state_1;
      32'd2: v__h3191 = state_2;
      32'd3: v__h3191 = state_3;
      32'd4: v__h3191 = state_4;
      32'd5: v__h3191 = state_5;
      32'd6: v__h3191 = state_6;
      32'd7: v__h3191 = state_7;
      32'd8: v__h3191 = state_8;
      32'd9: v__h3191 = state_9;
      32'd10: v__h3191 = state_10;
      32'd11: v__h3191 = state_11;
      32'd12: v__h3191 = state_12;
      32'd13: v__h3191 = state_13;
      32'd14: v__h3191 = state_14;
      32'd15: v__h3191 = state_15;
      default: v__h3191 = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(x__h2569 or
	  state_0 or
	  state_1 or
	  state_2 or
	  state_3 or
	  state_4 or
	  state_5 or
	  state_6 or
	  state_7 or
	  state_8 or
	  state_9 or
	  state_10 or
	  state_11 or state_12 or state_13 or state_14 or state_15)
  begin
    case (x__h2569)
      32'd0: z0__h2532 = state_0;
      32'd1: z0__h2532 = state_1;
      32'd2: z0__h2532 = state_2;
      32'd3: z0__h2532 = state_3;
      32'd4: z0__h2532 = state_4;
      32'd5: z0__h2532 = state_5;
      32'd6: z0__h2532 = state_6;
      32'd7: z0__h2532 = state_7;
      32'd8: z0__h2532 = state_8;
      32'd9: z0__h2532 = state_9;
      32'd10: z0__h2532 = state_10;
      32'd11: z0__h2532 = state_11;
      32'd12: z0__h2532 = state_12;
      32'd13: z0__h2532 = state_13;
      32'd14: z0__h2532 = state_14;
      32'd15: z0__h2532 = state_15;
      default: z0__h2532 = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  always@(x__h3283 or
	  state_0 or
	  state_1 or
	  state_2 or
	  state_3 or
	  state_4 or
	  state_5 or
	  state_6 or
	  state_7 or
	  state_8 or
	  state_9 or
	  state_10 or
	  state_11 or state_12 or state_13 or state_14 or state_15)
  begin
    case (x__h3283)
      32'd0: v__h3268 = state_0;
      32'd1: v__h3268 = state_1;
      32'd2: v__h3268 = state_2;
      32'd3: v__h3268 = state_3;
      32'd4: v__h3268 = state_4;
      32'd5: v__h3268 = state_5;
      32'd6: v__h3268 = state_6;
      32'd7: v__h3268 = state_7;
      32'd8: v__h3268 = state_8;
      32'd9: v__h3268 = state_9;
      32'd10: v__h3268 = state_10;
      32'd11: v__h3268 = state_11;
      32'd12: v__h3268 = state_12;
      32'd13: v__h3268 = state_13;
      32'd14: v__h3268 = state_14;
      32'd15: v__h3268 = state_15;
      default: v__h3268 = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (state_0$EN) state_0 <= `BSV_ASSIGNMENT_DELAY state_0$D_IN;
    if (state_1$EN) state_1 <= `BSV_ASSIGNMENT_DELAY state_1$D_IN;
    if (state_10$EN) state_10 <= `BSV_ASSIGNMENT_DELAY state_10$D_IN;
    if (state_11$EN) state_11 <= `BSV_ASSIGNMENT_DELAY state_11$D_IN;
    if (state_12$EN) state_12 <= `BSV_ASSIGNMENT_DELAY state_12$D_IN;
    if (state_13$EN) state_13 <= `BSV_ASSIGNMENT_DELAY state_13$D_IN;
    if (state_14$EN) state_14 <= `BSV_ASSIGNMENT_DELAY state_14$D_IN;
    if (state_15$EN) state_15 <= `BSV_ASSIGNMENT_DELAY state_15$D_IN;
    if (state_2$EN) state_2 <= `BSV_ASSIGNMENT_DELAY state_2$D_IN;
    if (state_3$EN) state_3 <= `BSV_ASSIGNMENT_DELAY state_3$D_IN;
    if (state_4$EN) state_4 <= `BSV_ASSIGNMENT_DELAY state_4$D_IN;
    if (state_5$EN) state_5 <= `BSV_ASSIGNMENT_DELAY state_5$D_IN;
    if (state_6$EN) state_6 <= `BSV_ASSIGNMENT_DELAY state_6$D_IN;
    if (state_7$EN) state_7 <= `BSV_ASSIGNMENT_DELAY state_7$D_IN;
    if (state_8$EN) state_8 <= `BSV_ASSIGNMENT_DELAY state_8$D_IN;
    if (state_9$EN) state_9 <= `BSV_ASSIGNMENT_DELAY state_9$D_IN;
    if (state_i$EN) state_i <= `BSV_ASSIGNMENT_DELAY state_i$D_IN;
    if (z0$EN) z0 <= `BSV_ASSIGNMENT_DELAY z0$D_IN;
    if (z1$EN) z1 <= `BSV_ASSIGNMENT_DELAY z1$D_IN;
    if (z2$EN) z2 <= `BSV_ASSIGNMENT_DELAY z2$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    state_0 = 32'hAAAAAAAA;
    state_1 = 32'hAAAAAAAA;
    state_10 = 32'hAAAAAAAA;
    state_11 = 32'hAAAAAAAA;
    state_12 = 32'hAAAAAAAA;
    state_13 = 32'hAAAAAAAA;
    state_14 = 32'hAAAAAAAA;
    state_15 = 32'hAAAAAAAA;
    state_2 = 32'hAAAAAAAA;
    state_3 = 32'hAAAAAAAA;
    state_4 = 32'hAAAAAAAA;
    state_5 = 32'hAAAAAAAA;
    state_6 = 32'hAAAAAAAA;
    state_7 = 32'hAAAAAAAA;
    state_8 = 32'hAAAAAAAA;
    state_9 = 32'hAAAAAAAA;
    state_i = 32'hAAAAAAAA;
    z0 = 32'hAAAAAAAA;
    z1 = 32'hAAAAAAAA;
    z2 = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkWellPRNG