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jeffng-orjeffng-or
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Updated infra to eventually support original and spreadsheet input
updated tests for LEF changes fixed verilog/sv output updated liberty to new infra black reformatting Signed-off-by: Jeff Ng <jeffng@precisioninno.com>
1 parent 8d7b566 commit 43af37c

37 files changed

+6094
-5293
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‎test/au/dprf_256x256.au‎

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‎test/au/dprf_256x32.au‎

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‎test/au/dprf_256x32_h.au‎

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‎test/au/dpsram_256x256.au‎

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‎test/au/dpsram_256x32.au‎

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‎test/au/dpsram_256x32_h.au‎

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‎test/au/sprf_256x256.au‎

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‎test/au/sprf_256x32.au‎

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‎test/au/sprf_256x32_h.au‎

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‎test/au/spsram_256x256.au‎

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Original file line numberDiff line numberDiff line change
@@ -4703,24 +4703,140 @@ MACRO spsram_256x256
47034703
RECT 0.000 83.424 0.024 83.448 ;
47044704
END
47054705
END we_in
4706-
PIN ce_in
4706+
PIN clk
47074707
DIRECTION INPUT ;
47084708
USE SIGNAL ;
47094709
SHAPE ABUTMENT ;
47104710
PORT
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LAYER M4 ;
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RECT 0.000 83.568 0.024 83.592 ;
47134713
END
4714-
END ce_in
4715-
PIN clk
4714+
END clk
4715+
PIN ce_in
47164716
DIRECTION INPUT ;
47174717
USE SIGNAL ;
47184718
SHAPE ABUTMENT ;
47194719
PORT
47204720
LAYER M4 ;
47214721
RECT 0.000 83.712 0.024 83.736 ;
47224722
END
4723-
END clk
4723+
END ce_in
4724+
PIN VDD
4725+
DIRECTION INOUT ;
4726+
USE POWER ;
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PORT
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RECT 0.048 83.328 33.202 83.424 ;
4838+
END
4839+
END VDD
47244840
PIN VSS
47254841
DIRECTION INOUT ;
47264842
USE GROUND ;
@@ -4838,122 +4954,6 @@ MACRO spsram_256x256
48384954
RECT 0.048 83.712 33.202 83.808 ;
48394955
END
48404956
END VSS
4841-
PIN VDD
4842-
DIRECTION INOUT ;
4843-
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PORT
4845-
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OBS
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LAYER M1 ;
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RECT 0 0 33.250 84.000 ;

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