fixed SV bbox bus msb; black formatting

Signed-off-by: Jeff Ng <jeffng@precisioninno.com>

Author: jeffng-or

__init__.py

@@ -1,2 +1,4 @@
 # To get relative imports to work
-import os, sys; sys.path.append(os.path.dirname(os.path.realpath(__file__)))
+import os, sys
+
+sys.path.append(os.path.dirname(os.path.realpath(__file__)))

test/au/spsram_256x256.au

@@ -5039,7 +5039,7 @@ module spsram_256x256
 endmodule
 (* blackbox *)
 module spsram_256x256 (
-   output reg [31:0] rd_out,
+   output reg [255:0] rd_out,
    input [7:0] addr_in,
    input we_in,
    input [255:0] wd_in,

test/physical_test.py

@@ -15,7 +15,6 @@ class PhysicalDataTest(unittest.TestCase):
     def setUp(self):
         """Sets up base_data with example config data"""
 
-
     def test_empty_physical(self):
         """Tests physical field defaults"""
 
@@ -39,7 +38,7 @@ def test_set_extents_and_snapping(self):
         # Can't snap before setting extents
         with self.assertRaises(Exception):
             physical.snap_to_grid(1000, 1000)
-            
+
         # Set extents and verify values
         physical.set_extents(width, height)
         self.assertEqual(physical.get_width(False), width)
@@ -73,13 +72,13 @@ def test_pin_pitches_exception(self):
         # Can't set pin pitches before setting height
         with self.assertRaises(Exception):
             physical.set_pin_pitches("bogus", num_pins, min_pin_pitch, y_offset)
-            
+
         # Try again after setting height
         physical.set_extents(height, height)
         physical.snap_to_grid(1, 1)
         with self.assertRaises(Exception):
             physical.set_pin_pitches("bogus", num_pins, min_pin_pitch, y_offset)
-    
-        
+
+
 if __name__ == "__main__":
     unittest.main()

test/sv_bbox_test.py

@@ -0,0 +1,76 @@
+#!/usr/bin/env python3
+
+import os
+import re
+import io
+import sys
+import unittest
+
+sys.path.append(os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "utils")))
+from single_port_ram_verilog_exporter import SinglePortRAMVerilogExporter
+from memory_factory import MemoryFactory
+from class_process import Process
+from timing_data import TimingData
+from test_utils import TestUtils
+
+
+class SVBBoxDataTest(unittest.TestCase):
+    """Unit test for SystemVerilog blackbox class"""
+
+    def setUp(self):
+        """Sets up base_data with example config data"""
+        self._process = Process(TestUtils.get_base_process_data())
+        self._timing_data = TimingData()
+        self._bus_re = re.compile(
+            "^\s*\S+\s+(?:reg)?\s*\[\s*(\d+)\:(\d+)\\s*]\s*(\S+)\s*\,"
+        )
+
+    def _extract_bus_msb(self, content):
+        msb_map = {}
+        in_strm = io.StringIO(content)
+
+        for line in in_strm:
+            result = self._bus_re.match(line)
+            if result:
+                msb = int(result.group(1))
+                bus_name = result.group(3)
+                msb_map[bus_name] = msb
+        return msb_map
+
+    def _check_bus_msb(self, mem_name, bus_name, bus_msb_map, exp_msb):
+        self.assertIn(bus_name, bus_msb_map)
+        self.assertEqual(
+            bus_msb_map[bus_name],
+            exp_msb,
+            f"msb's don't match for {bus_name} on {mem_name}: {bus_msb_map[bus_name]} {exp_msb}",
+        )
+
+    def _check_bbox(self, words, depth):
+        name = f"fakeram_16_{depth}"
+        mem = MemoryFactory.create(
+            name, words, depth, 4, "RAM", "SP", self._process, self._timing_data
+        )
+        exporter = SinglePortRAMVerilogExporter(mem)
+        strm = io.StringIO()
+        exporter.export_blackbox(strm)
+        content = strm.getvalue()
+        strm.close()
+        bus_msb_map = self._extract_bus_msb(content)
+        self._check_bus_msb(name, "rd_out", bus_msb_map, mem.get_data_bus_msb())
+        self._check_bus_msb(name, "wd_in", bus_msb_map, mem.get_data_bus_msb())
+        self._check_bus_msb(name, "addr_in", bus_msb_map, mem.get_addr_bus_msb())
+
+    def test_spsram_bbox(self):
+        """
+        Tests that the spsram rd_out and wd_in indices are the same and
+        correct
+        """
+
+        words = 16
+        depths = [32, 64, 256]
+        for depth in depths:
+            self._check_bbox(words, depth)
+
+
+if __name__ == "__main__":
+    unittest.main()

test/test_utils.py

@@ -2,6 +2,7 @@
 
 import os
 
+
 class TestUtils:
     @staticmethod
     def get_base_process_data():
@@ -31,7 +32,6 @@ def get_exec_name(exec_name):
 
         if "COVERAGE_RUN" in os.environ:
             exec_cmd = "coverage run --parallel-mode " + exec_name
-        else: #pragma: nocover
+        else:  # pragma: nocover
             exec_cmd = exec_name
         return exec_cmd
-        

utils/class_process.py

@@ -20,8 +20,8 @@ def __init__(self, json_data):
         self.pin_width_nm = int(json_data["pin_width_nm"])
         self.pin_pitch_nm = int(json_data["pin_pitch_nm"])
         self.metal_track_pitch_nm = int(json_data["metal_track_pitch_nm"])
-        self.contacted_poly_pitch_nm = int(json_data["contacted_poly_pitch_nm"])
-        self.fin_pitch_nm = int(json_data["fin_pitch_nm"])
+        self.contacted_poly_pitch_nm = json_data.get("contacted_poly_pitch_nm", None)
+        self.fin_pitch_nm = json_data.get("fin_pitch_nm", None)
         self.manufacturing_grid_nm = int(json_data["manufacturing_grid_nm"])
         self.column_mux_factor = int(json_data["column_mux_factor"])
 

utils/single_port_ram_verilog_exporter.py

@@ -116,7 +116,7 @@ def export_blackbox(self, out_fh):
         addr_bus_msb = mem.get_addr_bus_msb()
         data_bus_msb = mem.get_data_bus_msb()
         self.export_bb_header(out_fh)
-        out_fh.write(f"   output reg [31:0] rd_out,\n")
+        out_fh.write(f"   output reg [{data_bus_msb}:0] rd_out,\n")
         out_fh.write(f"   input [{addr_bus_msb}:0] addr_in,\n")
         out_fh.write("   input we_in,\n")
         out_fh.write(f"   input [{data_bus_msb}:0] wd_in,\n")