Error with verilator lint check process in latest Openlane's version

[CristopherA96]

Hi,

I am working with OpenFPGA files and when I run the flow the verilator_lint_check process showed me 2 errors.

Those errors are because some warnings about duplicated modules within pdks and inv_buf_passgate.v file, verilator_lint_check checks the pdks but OpenFPGA have generated a file called inv_buf_passgate.v, so how can I treat with this error if I need this file.

The log information at this stage is shown below:

%Warning-MODDUP: //openlane/designs/fpga_insts/cbx_1__0_/src/inv_buf_passgate.v: Duplicate declaration of module: 'sky130_fd_sc_hd__inv_1'
   59 | module sky130_fd_sc_hd__inv_1(A,
      |        ^~~~~~~~~~~~~~~~~~~~~~
                 //pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v: ... Location of original declaration
48362 | module sky130_fd_sc_hd__inv_1 (
      |        ^~~~~~~~~~~~~~~~~~~~~~
                 ... For warning description see https://verilator.org/warn/MODDUP?v=5.009
                 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message.
                 
                 
 I solved this warnings by disable RUN_VERILATOR variable.

[kareefardi]

This is a warning message. I believe there should be errors in the log different from these.

[CristopherA96]

Hi,

I think that this issue is because, OpenFPGA files contain some modules named as an standard cell of skywater (it is an standard cell), so when run_verilator process starts it breaks the flow because we are trying to get a netlist that has standard cells but in OpenFPGA we have also a module named equal as the standard cell in PDK.

I was thinking in changing the name of those modules but I am not sure if it will affect, because as I understood OF creates the files that contains some modules named as standard cells but those files are RTL not gate-level netlist, isn't it?