Using a slice of a multi-bit port as clock name

[scorbetta]

Dear,
my design (targeting Tiny Tapeout 06) has the following pinout:

    //...
    input wire [7:0] ui_in,
    input wire          clk,
    //...
);

and both clk and ui_in[0] are clocks for me. They are mesochronous clocks, but they do not have anything in common. clk is generated by an on-board RP2040 chip, while the ui_in[0] is generated by an external board mounting an FPGA. For my design, the ui_in[0] is the main clock, while clk is auxiliary for some debug.

Relevant portion of the config.tcl file looks like:

set ::env(CLOCK_NET) "clk ui_in\\\[0\\\]"
set ::env(CLOCK_PERIOD) 40
set ::env(CLOCK_PORT) "ui_in\\\[0\\\]"
set ::env(BASE_SDC_FILE) "$script_dir/project.sdc"

The project.sdc file is derived from the base.sdc. I modified the clock creation section as follows:

create_clock [ get_ports "clk" ]  -name rp2040_clk -period $::env(CLOCK_PERIOD)
create_clock [ get_ports "ui_in\\\[0\\\]" ]  -name fpga_clk -period $::env(CLOCK_PERIOD)
set_clock_groups -asynchronous -group { rp2040_clk } -group { fpga_clk }

It seems however, that clock defined as ui_in[0] is not supported by OpenLane. I get the following error:

[ERROR]: The specified clock port 'ui_in[0]' does not exist in the top-level module.

and I retraced it to the proper source being check_clock_ports.py. This script is invoked as follows within the synthesis.tcl script:

python3 $::env(SCRIPTS_DIR)/check_clock_ports.py \
   --top $::env(DESIGN_NAME) \
   --netlist-in $::env(synthesis_tmpfiles)/$::env(DESIGN_NAME).json \
   {*}$::env(CLOCK_PORT)]

And it searches for ui_in[0] within the JSON representation of the netlist (i.e., $::env(DESIGN_NAME).json). However, the ui_in port is a multi-bit port, and JSON does not flatten it, so there is no such ui_in[0], but only ui_in, with multi-bit attribute.

How can I solve this problem?

[urish]

I believe this was fixed by #2109