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transitioned Verilog list to wildcards #2769

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transitioned Verilog list to wildcards

transitioned Verilog list to wildcards #2769

Triggered via pull request July 15, 2025 14:56
@openroad-ciopenroad-ci
opened #3323
The-OpenROAD-Project-staging:is-int-wildcard
Status Success
Total duration 49s
Artifacts –

black.yaml

on: pull_request
lint
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