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transitioned Verilog list to wildcards #7858

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transitioned Verilog list to wildcards

transitioned Verilog list to wildcards #7858

Triggered via pull request July 15, 2025 14:56
@openroad-ciopenroad-ci
opened #3323
The-OpenROAD-Project-staging:is-int-wildcard
Status Success
Total duration 3m 29s
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github-actions-on-push.yml

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