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transitioned Verilog list to wildcards #1024

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transitioned Verilog list to wildcards

transitioned Verilog list to wildcards #1024

Triggered via pull request July 15, 2025 14:56
@openroad-ciopenroad-ci
opened #3323
The-OpenROAD-Project-staging:is-int-wildcard
Status Success
Total duration 22s
Artifacts –

github-actions-yaml-test.yml

on: pull_request
Tests for variables.yaml
14s
Tests for variables.yaml
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