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mock-alu: a number of updates after discussion of results
During the discussion below a number of additional investigations was done and knobs added to the code to allow for exploration. The-OpenROAD-Project/OpenROAD#3881 Signed-off-by: Øyvind Harboe <[email protected]>
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‎flow/designs/asap7/mock-alu/asap7.mk‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
export PLACE_DENSITY = 0.75
2+
export CORE_UTILIZATION = 50
3+
export CORNER = BC

‎flow/designs/asap7/mock-alu/config.mk‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,17 @@ export DESIGN_NICKNAME = mock-alu
55

66
export VERILOG_FILES = designs/src/mock-alu/*.v
77

8-
export SDC_FILE = designs/asap7/mock-alu/constraints.sdc
8+
export SDC_FILE = designs/asap7/mock-alu/constraints-$(PLATFORM).sdc
99

10-
export PLATFORM = asap7
10+
export PLATFORM ?= asap7
1111

12-
export PLACE_DENSITY = 0.75
13-
export CORE_UTILIZATION = 50
1412
export CORE_ASPECT_RATIO = 1
1513
export CORE_MARGIN = 2
1614

1715
verilog:
1816
export MOCK_ALU_WIDTH=$(word 1, $(MOCK_ALU_WIDTH)) ; \
1917
./designs/asap7/mock-alu/verilog.sh
18+
19+
include designs/asap7/mock-alu/$(PLATFORM).mk
20+
21+
export PLACE_PINS_ARGS=-annealing

‎flow/designs/asap7/mock-alu/constraints-asap7.sdc‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
set clk_name clock
2+
set clk_port_name clock
3+
set clk_period 100
4+
set clk_io_pct 0.2
5+
6+
set clk_port [get_ports $clk_port_name]
7+
8+
create_clock -name $clk_name -period $clk_period $clk_port
9+
10+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
11+
12+
set_input_delay [expr $clk_period * 0.7] -clock $clk_name $non_clock_inputs
13+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

flow/designs/asap7/mock-alu/constraints.sdc renamed to flow/designs/asap7/mock-alu/constraints-sky130hd.sdc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
set clk_name clock
22
set clk_port_name clock
3-
set clk_period 750
3+
set clk_period 5
44
set clk_io_pct 0.2
55

66
set clk_port [get_ports $clk_port_name]
@@ -10,4 +10,4 @@ create_clock -name $clk_name -period $clk_period $clk_port
1010
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
1111

1212
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13-
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
13+
set_output_delay [expr 0.2 * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/mock-alu/metadata-base-ok.json‎

Lines changed: 283 additions & 283 deletions
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‎flow/designs/asap7/mock-alu/rules-base.json‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -20,31 +20,31 @@
2020
"compare": "=="
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},
2222
"cts__timing__setup__ws": {
23-
"value": -199.73,
23+
"value": -640.59,
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"compare": ">="
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},
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"cts__timing__setup__ws__pre_repair": {
27-
"value": -517.62,
27+
"value": -737.7,
2828
"compare": ">="
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},
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"cts__timing__setup__ws__post_repair": {
31-
"value": -517.62,
31+
"value": -737.7,
3232
"compare": ">="
3333
},
3434
"cts__design__instance__count__setup_buffer": {
35-
"value": 100,
35+
"value": 603,
3636
"compare": "<="
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},
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"cts__design__instance__count__hold_buffer": {
39-
"value": 536,
39+
"value": 843,
4040
"compare": "<="
4141
},
4242
"globalroute__timing__clock__slack": {
43-
"value": -109.03,
43+
"value": -638.41,
4444
"compare": ">="
4545
},
4646
"globalroute__timing__setup__ws": {
47-
"value": -109.03,
47+
"value": -638.41,
4848
"compare": ">="
4949
},
5050
"detailedroute__route__wirelength": {
@@ -56,7 +56,7 @@
5656
"compare": "<="
5757
},
5858
"finish__timing__setup__ws": {
59-
"value": -100.67,
59+
"value": -597.82,
6060
"compare": ">="
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},
6262
"finish__design__instance__area": {
@@ -76,15 +76,15 @@
7676
"compare": ">="
7777
},
7878
"finish__timing__drv__setup_violation_count": {
79-
"value": 71,
79+
"value": 1610,
8080
"compare": "<="
8181
},
8282
"finish__timing__drv__hold_violation_count": {
83-
"value": 10,
83+
"value": 46,
8484
"compare": "<="
8585
},
8686
"finish__timing__wns_percent_delay": {
87-
"value": -10.0,
87+
"value": -97.4,
8888
"compare": ">="
8989
}
9090
}

‎flow/designs/asap7/mock-alu/sky130hd.mk‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
export PLACE_DENSITY = 0.50
2+
export CORE_UTILIZATION = 30

‎flow/designs/asap7/mock-alu/verilog.sh‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ cd ../../src/mock-alu
1212
rm -f *.v
1313

1414
sbt -Duser.home="$HOME" -Djline.terminal=jline.UnsupportedTerminal -batch \
15-
"test:runMain GenerateMockAlu --width ${MOCK_ALU_WIDTH} --operations ${MOCK_ALU_OPERATIONS} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
15+
"test:runMain GenerateMockAlu --width ${MOCK_ALU_WIDTH} --operations ${MOCK_ALU_OPERATIONS} --platform ${PLATFORM} -- --emit-modules verilog --emission-options disableMemRandomization,disableRegisterRandomization --target-dir ."
1616

1717
# reduce git noise as these comments will change if the line numbers in Chisel changes
1818
find . -name "*.v" -type f -exec sed -i 's/ \/\/.*$//' {} \;

‎flow/designs/src/mock-alu/BarrelShifter.v‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
module BarrelShifter(
22
input [63:0] io_data,
33
input [5:0] io_shiftAmount,
4-
input [4:0] io_dir,
4+
input [5:0] io_dir,
55
output [63:0] io_out
66
);
7-
wire _rotate_T = io_dir == 5'h8;
7+
wire _rotate_T = io_dir == 6'hb;
88
wire [6:0] _GEN_0 = {{1'd0}, io_shiftAmount};
99
wire [6:0] _rotate_T_2 = 7'h40 - _GEN_0;
1010
wire [6:0] rotate = _rotate_T ? _rotate_T_2 : {{1'd0}, io_shiftAmount};
1111
wire [63:0] _rotateInput_T_3 = io_data[63] ? 64'hffffffffffffffff : 64'h0;
12-
wire [63:0] _rotateInput_T_8 = 5'ha == io_dir ? _rotateInput_T_3 : 64'h0;
13-
wire [63:0] _rotateInput_T_10 = 5'h8 == io_dir ? io_data : _rotateInput_T_8;
14-
wire [63:0] _rotateInput_T_12 = 5'h9 == io_dir ? 64'h0 : _rotateInput_T_10;
12+
wire [63:0] _rotateInput_T_8 = 6'hd == io_dir ? _rotateInput_T_3 : 64'h0;
13+
wire [63:0] _rotateInput_T_10 = 6'hb == io_dir ? io_data : _rotateInput_T_8;
14+
wire [63:0] _rotateInput_T_12 = 6'hc == io_dir ? 64'h0 : _rotateInput_T_10;
1515
wire [63:0] _rotateInput_T_14 = _rotate_T ? 64'h0 : io_data;
1616
wire [127:0] rotateInput = {_rotateInput_T_12,_rotateInput_T_14};
1717
wire [127:0] _io_out_T = rotateInput >> rotate;

‎flow/designs/src/mock-alu/MockAlu.v‎

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,14 @@
11
module MockAlu(
22
input clock,
33
input reset,
4-
input [4:0] io_op,
4+
input [5:0] io_op,
55
input [63:0] io_a,
66
input [63:0] io_b,
77
output [63:0] io_out
88
);
99
wire [63:0] barrel_io_data;
1010
wire [5:0] barrel_io_shiftAmount;
11-
wire [4:0] barrel_io_dir;
11+
wire [5:0] barrel_io_dir;
1212
wire [63:0] barrel_io_out;
1313
wire [63:0] multResult_mult_a;
1414
wire [63:0] multResult_mult_b;
@@ -24,16 +24,16 @@ module MockAlu(
2424
wire [63:0] operand_2_io_a;
2525
wire [63:0] operand_2_io_b;
2626
wire [63:0] operand_2_io_out;
27-
reg [4:0] op;
27+
reg [5:0] op;
2828
reg [63:0] a;
2929
reg [63:0] b;
30-
wire _isSubtraction_T = op == 5'h4;
31-
wire _isSubtraction_T_1 = op == 5'hb;
32-
wire _isSubtraction_T_2 = op == 5'hc;
33-
wire _isSubtraction_T_3 = op == 5'hd;
34-
wire _isSubtraction_T_4 = op == 5'hf;
35-
wire _isSubtraction_T_5 = op == 5'he;
36-
wire _isSubtraction_T_6 = op == 5'h10;
30+
wire _isSubtraction_T = op == 6'h7;
31+
wire _isSubtraction_T_1 = op == 6'he;
32+
wire _isSubtraction_T_2 = op == 6'hf;
33+
wire _isSubtraction_T_3 = op == 6'h10;
34+
wire _isSubtraction_T_4 = op == 6'h12;
35+
wire _isSubtraction_T_5 = op == 6'h11;
36+
wire _isSubtraction_T_6 = op == 6'h13;
3737
wire isSubtraction = _isSubtraction_T | _isSubtraction_T_1 | _isSubtraction_T_2 | _isSubtraction_T_3 |
3838
_isSubtraction_T_4 | _isSubtraction_T_5 | _isSubtraction_T_6;
3939
wire [63:0] _modifiedB_T = ~b;
@@ -49,20 +49,20 @@ module MockAlu(
4949
wire _T_4 = isTrueZero | isNegative;
5050
wire _T_5 = ~carryOut;
5151
wire _T_7 = isTrueZero | _T_5;
52-
wire [63:0] _io_out_T_2 = 5'h5 == op ? operand_io_out : 64'h0;
53-
wire [63:0] _io_out_T_4 = 5'h6 == op ? operand_1_io_out : _io_out_T_2;
54-
wire [63:0] _io_out_T_6 = 5'h7 == op ? operand_2_io_out : _io_out_T_4;
55-
wire [63:0] _io_out_T_8 = 5'h0 == op ? result : _io_out_T_6;
56-
wire [63:0] _io_out_T_10 = 5'h4 == op ? result : _io_out_T_8;
57-
wire [63:0] _io_out_T_12 = 5'hb == op ? {{63'd0}, isTrueZero} : _io_out_T_10;
58-
wire [63:0] _io_out_T_14 = 5'hc == op ? {{63'd0}, _T_3} : _io_out_T_12;
59-
wire [63:0] _io_out_T_16 = 5'hd == op ? {{63'd0}, isNegative} : _io_out_T_14;
60-
wire [63:0] _io_out_T_18 = 5'hf == op ? {{63'd0}, _T_4} : _io_out_T_16;
61-
wire [63:0] _io_out_T_20 = 5'he == op ? {{63'd0}, _T_5} : _io_out_T_18;
62-
wire [63:0] _io_out_T_22 = 5'h10 == op ? {{63'd0}, _T_7} : _io_out_T_20;
63-
wire [63:0] _io_out_T_24 = 5'h8 == op ? barrel_io_out : _io_out_T_22;
64-
wire [63:0] _io_out_T_26 = 5'h9 == op ? barrel_io_out : _io_out_T_24;
65-
wire [63:0] _io_out_T_28 = 5'ha == op ? barrel_io_out : _io_out_T_26;
52+
wire [63:0] _io_out_T_2 = 6'h8 == op ? operand_io_out : 64'h0;
53+
wire [63:0] _io_out_T_4 = 6'h9 == op ? operand_1_io_out : _io_out_T_2;
54+
wire [63:0] _io_out_T_6 = 6'ha == op ? operand_2_io_out : _io_out_T_4;
55+
wire [63:0] _io_out_T_8 = 6'h0 == op ? result : _io_out_T_6;
56+
wire [63:0] _io_out_T_10 = 6'h7 == op ? result : _io_out_T_8;
57+
wire [63:0] _io_out_T_12 = 6'he == op ? {{63'd0}, isTrueZero} : _io_out_T_10;
58+
wire [63:0] _io_out_T_14 = 6'hf == op ? {{63'd0}, _T_3} : _io_out_T_12;
59+
wire [63:0] _io_out_T_16 = 6'h10 == op ? {{63'd0}, isNegative} : _io_out_T_14;
60+
wire [63:0] _io_out_T_18 = 6'h12 == op ? {{63'd0}, _T_4} : _io_out_T_16;
61+
wire [63:0] _io_out_T_20 = 6'h11 == op ? {{63'd0}, _T_5} : _io_out_T_18;
62+
wire [63:0] _io_out_T_22 = 6'h13 == op ? {{63'd0}, _T_7} : _io_out_T_20;
63+
wire [63:0] _io_out_T_24 = 6'hb == op ? barrel_io_out : _io_out_T_22;
64+
wire [63:0] _io_out_T_26 = 6'hc == op ? barrel_io_out : _io_out_T_24;
65+
wire [63:0] _io_out_T_28 = 6'hd == op ? barrel_io_out : _io_out_T_26;
6666
reg [127:0] io_out_REG;
6767
BarrelShifter barrel (
6868
.io_data(barrel_io_data),
@@ -98,7 +98,7 @@ module MockAlu(
9898
op <= io_op;
9999
a <= io_a;
100100
b <= io_b;
101-
if (5'h11 == op) begin
101+
if (6'h14 == op) begin
102102
io_out_REG <= multResult_mult_o;
103103
end else begin
104104
io_out_REG <= {{64'd0}, _io_out_T_28};

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