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lint flow/designs
Signed-off-by: Jack Luar <[email protected]>
1 parent 124805b commit 04cf9bc

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28 files changed

+3396
-1704
lines changed

28 files changed

+3396
-1704
lines changed

‎flow/designs/asap7/cva6/constraint.sdc‎

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -14,15 +14,23 @@ create_clock [get_ports $clk_port] -name $clk_name -period $clk_period
1414
# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].data_sram
1515
# set_dont_touch i_cache_subsystem/i_cva6_icache/gen_sram[*].tag_sram
1616
# #constraint the timing to and from the sram black boxes
17-
# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
18-
# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
19-
# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
20-
# set_input_delay -clock main_clk -max $input_delay i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
17+
# set_input_delay -clock main_clk -max $input_delay \
18+
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
19+
# set_input_delay -clock main_clk -max $input_delay \
20+
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
21+
# set_input_delay -clock main_clk -max $input_delay \
22+
# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
23+
# set_input_delay -clock main_clk -max $input_delay \
24+
# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/rdata_o[*]
2125

22-
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
23-
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
24-
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
25-
# set_output_delay $output_delay -max -clock main_clk i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
26+
# set_output_delay $output_delay -max -clock main_clk \
27+
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_tag_srams_*__i_tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
28+
# set_output_delay $output_delay -max -clock main_clk \
29+
# i_cache_subsystem/i_wt_dcache/i_wt_dcache_mem/gen_data_banks_*__i_data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
30+
# set_output_delay $output_delay -max -clock main_clk \
31+
# i_cache_subsystem/i_cva6_icache/gen_sram_*__data_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
32+
# set_output_delay $output_delay -max -clock main_clk \
33+
# i_cache_subsystem/i_cva6_icache/gen_sram_*__tag_sram/gen_cut_*__gen_mem_i_tc_sram_wrapper/addr_i[*]
2634

2735

2836
set_false_path -to [get_ports {rvfi_probes_o}]

‎flow/designs/asap7/mock-array/macro-placement.tcl‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,9 @@ for { set i 0 } { $i < 8 } { incr i } {
2020
set macro_name [format "ces_%d_%d" $i $j]
2121
set x_location [expr { $j * $x_pitch + $x_offset }]
2222
set y_location [expr { $i * $y_pitch + $y_offset }]
23-
place_macro -macro_name $macro_name -location [list [expr [ord::dbu_to_microns 1] * $x_location] [expr [ord::dbu_to_microns 1] * $y_location]] -orientation R0
23+
place_macro -macro_name $macro_name -location \
24+
[list [expr [ord::dbu_to_microns 1] * $x_location] \
25+
[expr [ord::dbu_to_microns 1] * $y_location]] \
26+
-orientation R0
2427
}
2528
}

‎flow/designs/asap7/mock-array/power.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -114,7 +114,8 @@ if { $total_power_vcd == $total_power_user_activity } {
114114
}
115115

116116
if { abs($total_power_vcd - $total_power_user_activity) > 1e-3 } {
117-
puts "Error: Total power mismatch between VCD and user activity: $total_power_vcd vs $total_power_user_activity"
117+
puts "Error: Total power mismatch between VCD and user activity: \
118+
$total_power_vcd vs $total_power_user_activity"
118119
exit 1
119120
}
120121

‎flow/designs/asap7/mock-cpu/constraint.sdc‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,13 @@ set clk_period 333
1010
set clk2_period 1000
1111

1212
set clk1_name clk
13-
create_clock -name $clk1_name -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk1_name]
13+
create_clock -name $clk1_name -period $clk_period -waveform \
14+
[list 0 [expr $clk_period/2]] [get_ports $clk1_name]
1415
set_clock_uncertainty 10 [get_clocks $clk1_name]
1516

1617
set clk2_name clk_uncore
17-
create_clock -name $clk2_name -period $clk2_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk2_name]
18+
create_clock -name $clk2_name -period $clk2_period -waveform \
19+
[list 0 [expr $clk_period/2]] [get_ports $clk2_name]
1820
set_clock_uncertainty 10 [get_clocks $clk2_name]
1921
set_clock_groups -group $clk1_name -group $clk2_name -asynchronous -allow_paths
2022

‎flow/designs/asap7/mock-cpu/io.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,4 +6,5 @@ foreach prefix {"" flow/} {
66
}
77
}
88

9-
set_io_pin_constraint -order -group -region bottom:* -pin_names [concat [match_pins .*] [match_pins clk input 1]]
9+
set_io_pin_constraint -order -group -region bottom:* \
10+
-pin_names [concat [match_pins .*] [match_pins clk input 1]]

‎flow/designs/gf12/ariane/io.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1,2 @@
1-
exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* -region top:* -region bottom:*
1+
exclude_io_pin_region -region left:0-150 -region left:450-600 -region right:* \
2+
-region top:* -region bottom:*

‎flow/designs/gf12/ariane133/io.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1,2 @@
1-
exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* -region top:* -region bottom:*
1+
exclude_io_pin_region -region left:0-200 -region left:500-700 -region right:* \
2+
-region top:* -region bottom:*

‎flow/designs/gf12/bp_single/fastroute.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,4 +3,5 @@ set_global_routing_layer_adjustment M3 0.6
33
set_global_routing_layer_adjustment C4-C5 0.5
44
set_global_routing_layer_adjustment K1-K4 0.45
55

6-
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) -clock K1-$::env(MAX_ROUTING_LAYER)
6+
set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) \
7+
-clock K1-$::env(MAX_ROUTING_LAYER)

‎flow/designs/gf12/ca53/io.tcl‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1 +1,2 @@
1-
exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* -region top:* -region bottom:*
1+
exclude_io_pin_region -region left:0-600 -region left:1350-1400 -region right:* \
2+
-region top:* -region bottom:*

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