synth: add SYNTH_MOCK_LARGE_MEMORIES

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/designs/sky130hd/microwatt/config.mk

@@ -36,7 +36,4 @@ export SETUP_SLACK_MARGIN = 0.2
 # GRT non-default config
 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/fastroute.tcl
 
-# This is high, some SRAMs should probably be converted
-# to real SRAMs and not instantiated as flops
-export SYNTH_MEMORY_MAX_BITS = 42000
-
+export SYNTH_MOCK_LARGE_MEMORIES = 1

flow/scripts/synth.tcl

@@ -55,6 +55,20 @@ if { !$::env(SYNTH_HIERARCHICAL) } {
   synth -flatten -run coarse:fine {*}$synth_full_args
 }
 
+
+if { $::env(SYNTH_MOCK_LARGE_MEMORIES) } {
+  foreach module [get_modules] {
+    foreach mem [get_memories $module] {
+      set size [memory_get $module $mem SIZE]
+
+      if {$size > $::env(SYNTH_MEMORY_MAX_BITS)} {
+          memory_set $module $mem SIZE 1
+          puts "Shrunk memory $mem in module $module from $size to 1"
+      }
+    }
+  }
+}
+
 json -o $::env(RESULTS_DIR)/mem.json
 # Run report and check here so as to fail early if this synthesis run is doomed
 exec -- $::env(PYTHON_EXE) $::env(SCRIPTS_DIR)/mem_dump.py \

flow/scripts/variables.yaml

@@ -177,6 +177,22 @@ SYNTH_MEMORY_MAX_BITS:
   default: 4096
   stages:
     - synth
+SYNTH_MOCK_LARGE_MEMORIES:
+  description: >
+    Reduce memories larger than SYNTH_MEMORY_MAX_BITS to 1 row.
+
+    This is useful to separate the concern of instantiating and placing
+    memories from investigating other issues with a design.
+
+    Memories with a single 1 row will of course have unrealistically good
+    timing and area characteristics, but timing will still correctly terminate
+    in a register.
+
+    Also, large port memories, typically register files, will still have the
+    retain a lot of the port logic that can be useful to investigate issues.
+  default: 0
+  stages:
+    - synth
 SYNTH_HDL_FRONTEND:
   description: >
     Select an alternative language frontend to ingest the design. Available option