Skip to content

Commit 0719564

Browse files
malibertymaliberty
authored
Merge pull request #1403 from Pinata-Consulting/block-mock
makefile: BLOCKS workflow to quickly set up a CI flow for a new design and refine incrementally
2 parents 027ced4 + 6f18cb2 commit 0719564

File tree

12 files changed

+738
-4
lines changed

12 files changed

+738
-4
lines changed

‎flow/Makefile‎

Lines changed: 16 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -207,7 +207,6 @@ ifeq ($(MAKELEVEL),0)
207207
$(info [INFO][FLOW] Invoked hierarchical flow.)
208208
$(foreach block,$(BLOCKS),$(info Block ${block} needs to be hardened.))
209209
endif
210-
$(foreach block,$(BLOCKS),$(eval BLOCK_CONFIGS += ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(block)/config.mk))
211210
$(foreach block,$(BLOCKS),$(eval BLOCK_LEFS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lef))
212211
$(foreach block,$(BLOCKS),$(eval BLOCK_LIBS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/${block}.lib))
213212
$(foreach block,$(BLOCKS),$(eval BLOCK_GDS += ./results/$(PLATFORM)/$(DESIGN_NICKNAME)_$(block)/$(FLOW_VARIANT)/6_final.gds))
@@ -313,9 +312,23 @@ endif
313312
export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT)))
314313

315314
define GENERATE_ABSTRACT_RULE
316-
# Single rule, two targets, hence the "&:", syntax
315+
ifeq ($(wildcard $(3)),)
316+
# There is no unqiue config.mk for this module, use the shared
317+
# block.mk that, by convention, is in the same folder as config.mk
318+
# of the parent macro.
319+
#
320+
# At an early stage, before refining each of the macros, a shared
321+
# block.mk file can be useful to run through the flow to explore
322+
# more global concerns instead of getting mired in the details of
323+
# each macro.
324+
block := $(patsubst ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/%,%,$(dir $(3)))
325+
$(1) $(2) &: ./designs/$$(PLATFORM)/$$(DESIGN_NICKNAME)/block.mk
326+
$$(UNSET_AND_MAKE) DESIGN_NAME=${block} DESIGN_NICKNAME=$$(DESIGN_NICKNAME)_${block} DESIGN_CONFIG=$$< generate_abstract
327+
else
328+
# There is a unqiue config.mk for this Verilog module
317329
$(1) $(2) &: $(3)
318-
$$(UNSET_AND_MAKE) DESIGN_CONFIG=$(3) generate_abstract
330+
$$(UNSET_AND_MAKE) DESIGN_CONFIG=$$< generate_abstract
331+
endif
319332
endef
320333

321334
# Targets to harden Blocks in case of hierarchical flow is triggered

‎flow/designs/asap7/aes-block/autotuner.json‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
{
2+
"_SDC_FILE_PATH": "constraint.sdc",
3+
"_SDC_CLK_PERIOD": {
4+
"type": "float",
5+
"minmax": [
6+
100,
7+
600
8+
],
9+
"step": 0
10+
},
11+
"CORE_UTILIZATION": {
12+
"type": "int",
13+
"minmax": [
14+
30,
15+
100
16+
],
17+
"step": 1
18+
},
19+
"CORE_ASPECT_RATIO": {
20+
"type": "float",
21+
"minmax": [
22+
0.5,
23+
2.0
24+
],
25+
"step": 0
26+
},
27+
"CORE_MARGIN": {
28+
"type": "int",
29+
"minmax": [
30+
2,
31+
2
32+
],
33+
"step": 0
34+
},
35+
"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
36+
"type": "int",
37+
"minmax": [
38+
0,
39+
5
40+
],
41+
"step": 1
42+
},
43+
"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
44+
"type": "int",
45+
"minmax": [
46+
0,
47+
5
48+
],
49+
"step": 1
50+
},
51+
"_FR_LAYER_ADJUST": {
52+
"type": "float",
53+
"minmax": [
54+
0.1,
55+
0.7
56+
],
57+
"step": 0
58+
},
59+
"PLACE_DENSITY_LB_ADDON": {
60+
"type": "float",
61+
"minmax": [
62+
0.0,
63+
0.99
64+
],
65+
"step": 0
66+
},
67+
"_PINS_DISTANCE": {
68+
"type": "int",
69+
"minmax": [
70+
1,
71+
4
72+
],
73+
"step": 1
74+
},
75+
"CTS_CLUSTER_SIZE": {
76+
"type": "int",
77+
"minmax": [
78+
10,
79+
200
80+
],
81+
"step": 1
82+
},
83+
"CTS_CLUSTER_DIAMETER": {
84+
"type": "int",
85+
"minmax": [
86+
20,
87+
400
88+
],
89+
"step": 1
90+
},
91+
"_FR_FILE_PATH": "",
92+
"_FR_GR_OVERFLOW": {
93+
"type": "int",
94+
"minmax": [
95+
1,
96+
1
97+
],
98+
"step": 0
99+
}
100+
}

‎flow/designs/asap7/aes-block/block.mk‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
export PLATFORM = asap7
2+
3+
export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
4+
export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc
5+
6+
export ABC_AREA = 1
7+
8+
export CORE_UTILIZATION = 40
9+
export CORE_ASPECT_RATIO = 1
10+
export CORE_MARGIN = 2
11+
export PLACE_DENSITY = 0.70
12+
13+
export PLACE_PINS_ARGS = -annealing
14+

‎flow/designs/asap7/aes-block/config.mk‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
export PLATFORM = asap7
2+
3+
export DESIGN_NAME = aes_cipher_top
4+
export DESIGN_NICKNAME = aes-block
5+
6+
export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
7+
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
8+
9+
export ABC_AREA = 1
10+
11+
export CORE_UTILIZATION = 20
12+
export CORE_ASPECT_RATIO = 1
13+
export CORE_MARGIN = 2
14+
export PLACE_DENSITY = 0.65
15+
16+
export BLOCKS = aes_rcon aes_sbox
17+
export SYNTH_HIERARCHICAL = 1
18+
export RTLMP_FLOW = True
19+
20+
export PLACE_PINS_ARGS = -annealing
21+
22+
# Generous routing at top level
23+
export MIN_ROUTING_LAYER = M2
24+
export MAX_ROUTING_LAYER = M9
25+
26+
# Ignore power at this exploratory level
27+
export GND_NETS_VOLTAGES = ""
28+
export PWR_NETS_VOLTAGES = ""

‎flow/designs/asap7/aes-block/constraint.sdc‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
set clk_name clk
2+
set clk_port_name clk
3+
set clk_period 400
4+
set clk_io_pct 0.2
5+
6+
set clk_port [get_ports $clk_port_name]
7+
8+
create_clock -name $clk_name -period $clk_period $clk_port
9+
10+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
11+
12+
set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
13+
set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

0 commit comments

Comments
 (0)