Merge pull request #731 from The-OpenROAD-Project-staging/secure-ratchet_priv

Update clk constraints for priv platform designs -- Update metadata a…

Author: ravi-varadarajan

flow/designs/gf12/aes/constraint.sdc

@@ -2,7 +2,7 @@ current_design aes_cipher_top
 
 set clk_name  clk
 set clk_port_name clk
-set clk_period 460 
+set clk_period 420 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/gf12/aes/metadata-base-ok.json

@@ -8,7 +8,7 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 6213,
+        "value": 6209,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -48,15 +48,15 @@
         "compare": ">="
     },
     "detailedroute__route__wirelength": {
-        "value": 164717,
+        "value": 164282,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
         "value": 0,
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": 0.0,
+        "value": -25.76,
         "compare": ">="
     },
     "finish__design__instance__area": {

flow/designs/gf12/aes/rules-base.json

@@ -2,7 +2,7 @@ current_design gcd
 
 set clk_name  core_clock
 set clk_port_name clk
-set clk_period 310 
+set clk_period 280 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/gf12/gcd/constraint.sdc

@@ -2,7 +2,7 @@ current_design ibex_core
 
 set clk_name  core_clock
 set clk_port_name clk_i
-set clk_period 1100 
+set clk_period 1020 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]

flow/designs/gf12/gcd/metadata-base-ok.json

@@ -8,11 +8,11 @@
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 7891,
+        "value": 7887,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 16632,
+        "value": 16619,
         "compare": "<="
     },
     "detailedplace__design__violations": {
@@ -36,15 +36,15 @@
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 1891,
+        "value": 1672,
         "compare": "<="
     },
     "globalroute__timing__clock__slack": {
-        "value": -130.21,
+        "value": -98.01,
         "compare": ">="
     },
     "globalroute__timing__setup__ws": {
-        "value": -130.22,
+        "value": -98.02,
         "compare": ">="
     },
     "detailedroute__route__wirelength": {

flow/designs/gf12/ibex/constraint.sdc

@@ -2,7 +2,7 @@ current_design jpeg_encoder
 
 set clk_name  clk
 set clk_port_name clk
-set clk_period 840 
+set clk_period 770 
 set clk_io_pct 0.2
 
 set clk_port [get_ports $clk_port_name]