Move repair_tie_fanout to floorplan.tcl

Covers the rare case of a tie cell connected to multiple buffers each
driving an output.  You want to split up the tie cell before removing the
buffers.

Signed-off-by: Matt Liberty <[email protected]>

Author: maliberty

docs/user/FlowVariables.md

@@ -320,6 +320,8 @@ configuration file.
 - [SKIP_PIN_SWAP](#SKIP_PIN_SWAP)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [TAPCELL_TCL](#TAPCELL_TCL)
+- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
+- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## place variables
@@ -340,8 +342,6 @@ configuration file.
 - [PLACE_PINS_ARGS](#PLACE_PINS_ARGS)
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
-- [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
-- [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
 
 ## cts variables
 

flow/scripts/floorplan.tcl

@@ -103,6 +103,10 @@ if {[env_var_exists_and_non_empty FOOTPRINT_TCL]} {
   log_cmd source $::env(FOOTPRINT_TCL)
 }
 
+# This needs to come before any call to remove_buffers.  You could have one
+# tie driving multiple buffers that drive multiple outputs.
+repair_tie_fanout_helper
+
 if { [env_var_equals REMOVE_ABC_BUFFERS 1] } {
   # remove buffers inserted by yosys/abc
   remove_buffers

flow/scripts/resize.tcl

@@ -12,26 +12,6 @@ set_dont_use $::env(DONT_USE_CELLS)
 
 repair_design_helper
 
-if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
-  set tie_separation $env(TIE_SEPARATION)
-} else {
-  set tie_separation 0
-}
-
-# Repair tie lo fanout
-puts "Repair tie lo fanout..."
-set tielo_cell_name [lindex $env(TIELO_CELL_AND_PORT) 0]
-set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $env(TIELO_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $tie_separation $tielo_pin
-
-# Repair tie hi fanout
-puts "Repair tie hi fanout..."
-set tiehi_cell_name [lindex $env(TIEHI_CELL_AND_PORT) 0]
-set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $env(TIEHI_CELL_AND_PORT) 1]
-repair_tie_fanout -separation $tie_separation $tiehi_pin
-
 # hold violations are not repaired until after CTS
 
 # post report

flow/scripts/util.tcl

@@ -13,6 +13,28 @@ proc log_cmd {cmd args} {
   return $result
 }
 
+proc repair_tie_fanout_helper {} {
+  if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
+    set tie_separation $env(TIE_SEPARATION)
+  } else {
+    set tie_separation 0
+  }
+
+  # Repair tie lo fanout
+  puts "Repair tie lo fanout..."
+  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $tie_separation $tielo_pin
+
+  # Repair tie hi fanout
+  puts "Repair tie hi fanout..."
+  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+  repair_tie_fanout -separation $tie_separation $tiehi_pin
+}
+
 proc fast_route {} {
   if {[env_var_exists_and_non_empty FASTROUTE_TCL]} {
     log_cmd source $::env(FASTROUTE_TCL)

flow/scripts/variables.yaml

@@ -214,13 +214,13 @@ TIEHI_CELL_AND_PORT:
     Netlist.
   stages:
     - synth
-    - place
+    - floorplan
 TIELO_CELL_AND_PORT:
   description: |
     Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.
   stages:
     - synth
-    - place
+    - floorplan
 MIN_BUF_CELL_AND_PORTS:
   description: |
     Used to insert a buffer cell to pass through wires. Used in synthesis.