makefile: remove single openroad invocation to run through all stages

This capability does not have CI tests and has rotted, clean it out to
clarify the code.

Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

flow/Makefile

@@ -968,9 +968,7 @@ clean_finish:
 # ==============================================================================
 
 .PHONY: all
-all: $(SDC_FILE) $(WRAPPED_LIBS) $(DONT_USE_LIBS) $(OBJECTS_DIR)/klayout.lyt $(WRAPPED_GDSOAS) $(DONT_USE_SC_LIB)
-	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/run_all.tcl -metrics $(LOG_DIR)/run_all.json) 2>&1 | tee $(LOG_DIR)/run_all.log
+all: synth floorplan place cts route finish
 
 .PHONY: clean
 clean:

flow/scripts/generate_abstract.tcl

@@ -27,7 +27,3 @@ if {[info exist ::env(CDL_FILES)]} {
   cdl read_masters $::env(CDL_FILES)
   cdl out $::env(RESULTS_DIR)/$stem.cdl
 }
-
-if {![info exists standalone] || $standalone} {
-  exit
-}

flow/scripts/load.tcl

@@ -1,37 +1,33 @@
 proc load_design {design_file sdc_file msg} {
-  if {![info exists standalone] || $standalone} {
-    # Read liberty files
-    source $::env(SCRIPTS_DIR)/read_liberty.tcl
-
-    # Read design files
-    set ext [file extension $design_file]
-    if {$ext == ".v"} {
-      read_lef $::env(TECH_LEF)
-      read_lef $::env(SC_LEF)
-      if {[info exist ::env(ADDITIONAL_LEFS)]} {
-        foreach lef $::env(ADDITIONAL_LEFS) {
-          read_lef $lef
-        }
+  # Read liberty files
+  source $::env(SCRIPTS_DIR)/read_liberty.tcl
+
+  # Read design files
+  set ext [file extension $design_file]
+  if {$ext == ".v"} {
+    read_lef $::env(TECH_LEF)
+    read_lef $::env(SC_LEF)
+    if {[info exist ::env(ADDITIONAL_LEFS)]} {
+      foreach lef $::env(ADDITIONAL_LEFS) {
+        read_lef $lef
       }
-      read_verilog $::env(RESULTS_DIR)/$design_file
-      link_design $::env(DESIGN_NAME)
-    } elseif {$ext == ".odb"} {
-      read_db $::env(RESULTS_DIR)/$design_file
-    } else {
-      error "Unrecognized input file $design_file"
     }
+    read_verilog $::env(RESULTS_DIR)/$design_file
+    link_design $::env(DESIGN_NAME)
+  } elseif {$ext == ".odb"} {
+    read_db $::env(RESULTS_DIR)/$design_file
+  } else {
+    error "Unrecognized input file $design_file"
+  }
 
-    # Read SDC file
-    read_sdc $::env(RESULTS_DIR)/$sdc_file
+  # Read SDC file
+  read_sdc $::env(RESULTS_DIR)/$sdc_file
 
-    if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
-      source $::env(PLATFORM_DIR)/derate.tcl
-    }
-
-    source $::env(PLATFORM_DIR)/setRC.tcl
-  } else {
-    puts $msg
+  if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
+    source $::env(PLATFORM_DIR)/derate.tcl
   }
+
+  source $::env(PLATFORM_DIR)/setRC.tcl
 }
 
 #===========================================================================================