Merge pull request #3141 from jeffng-or/synth-preamble-verific

Added yosys/verific support to synth_preamble

Author: maliberty

flow/designs/asap7/cva6/rules-base.json

@@ -1,14 +1,14 @@
 {
     "synth__design__instance__area__stdcell": {
-        "value": 13337.62,
+        "value": 16477.72,
         "compare": "<="
     },
     "constraints__clocks__count": {
         "value": 1,
         "compare": "=="
     },
     "placeopt__design__instance__area": {
-        "value": 15798,
+        "value": 19790,
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
@@ -32,7 +32,7 @@
         "compare": "<="
     },
     "detailedroute__route__wirelength": {
-        "value": 1241141,
+        "value": 1466793,
         "compare": "<="
     },
     "detailedroute__route__drc_errors": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "finish__design__instance__area": {
-        "value": 16112,
+        "value": 20112,
         "compare": "<="
     },
     "finish__timing__drv__setup_violation_count": {

flow/designs/nangate45/mempool_group/rules-base.json

@@ -0,0 +1,70 @@
+{
+    "synth__design__instance__area__stdcell": {
+        "value": 271098.37,
+        "compare": "<="
+    },
+    "constraints__clocks__count": {
+        "value": 2,
+        "compare": "=="
+    },
+    "placeopt__design__instance__area": {
+        "value": 322046,
+        "compare": "<="
+    },
+    "placeopt__design__instance__count__stdcell": {
+        "value": 163160,
+        "compare": "<="
+    },
+    "detailedplace__design__violations": {
+        "value": 0,
+        "compare": "=="
+    },
+    "cts__design__instance__count__setup_buffer": {
+        "value": 11373,
+        "compare": "<="
+    },
+    "cts__design__instance__count__hold_buffer": {
+        "value": 11373,
+        "compare": "<="
+    },
+    "globalroute__antenna_diodes_count": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__route__wirelength": {
+        "value": 4942626,
+        "compare": "<="
+    },
+    "detailedroute__route__drc_errors": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna__violating__nets": {
+        "value": 0,
+        "compare": "<="
+    },
+    "detailedroute__antenna_diodes_count": {
+        "value": 5,
+        "compare": "<="
+    },
+    "finish__timing__setup__ws": {
+        "value": -2.35,
+        "compare": ">="
+    },
+    "finish__design__instance__area": {
+        "value": 331160,
+        "compare": "<="
+    },
+    "finish__timing__drv__setup_violation_count": {
+        "value": 7094,
+        "compare": "<="
+    },
+    "finish__timing__drv__hold_violation_count": {
+        "value": 100,
+        "compare": "<="
+    },
+    "finish__timing__wns_percent_delay": {
+        "value": -109.25,
+        "compare": ">="
+    }
+}

flow/scripts/synth_preamble.tcl

@@ -51,6 +51,14 @@ proc read_design_sources {} {
       {*}$vIdirsArgs {*}$::env(VERILOG_FILES) {*}$::env(VERILOG_DEFINES)
     # Workaround for yosys-slang#119
     setattr -unset init
+  } elseif {[env_var_equals SYNTH_HDL_FRONTEND verific]} {
+    if {[env_var_exists_and_non_empty VERILOG_INCLUDE_DIRS]} {
+	verific -vlog-incdir {*}$::env(VERILOG_INCLUDE_DIRS)
+    }
+    if {[env_var_exists_and_non_empty VERILOG_DEFINES]} {
+	verific -vlog-define {*}$::env(VERILOG_DEFINES)
+    }
+    verific -sv2012 {*}$::env(VERILOG_FILES)
   } elseif {![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND]} {
     verilog_defaults -push
     verilog_defaults -add {*}$::env(VERILOG_DEFINES)