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lines changed Original file line number Diff line number Diff line change @@ -94,13 +94,15 @@ CORE_UTILIZATION:
9494 The core utilization percentage (0-100).
9595 stages :
9696 - floorplan
97+ tunable : 1
9798CORE_AREA :
9899 description : >
99100 The core area specified as a list of lower-left and upper-right corners in
100101 microns
101102 (X1 Y1 X2 Y2).
102103 stages :
103104 - floorplan
105+ tunable : 1
104106REPORT_CLOCK_SKEW :
105107 description : >
106108 Report clock skew as part of reporting metrics, starting at CTS, before which
@@ -337,6 +339,7 @@ CELL_PAD_IN_SITES_DETAIL_PLACEMENT:
337339 - cts
338340 - grt
339341 default : 0
342+ tunable : 1
340343PLACE_PINS_ARGS :
341344 description : |
342345 Arguments to place_pins
@@ -358,6 +361,7 @@ PLACE_DENSITY_LB_ADDON:
358361 stages :
359362 - floorplan
360363 - place
364+ tunable : 1
361365REPAIR_PDN_VIA_LAYER :
362366 description : |
363367 Remove power grid vias which generate DRC violations after detailed routing.
@@ -644,13 +648,15 @@ CORE_MARGIN:
644648 is undefined.
645649 stages :
646650 - floorplan
651+ tunable : 1
647652DIE_AREA :
648653 description : >
649654 The die area specified as a list of lower-left and upper-right corners in
650655 microns
651656 (X1 Y1 X2 Y2).
652657 stages :
653658 - floorplan
659+ tunable : 1
654660RESYNTH_AREA_RECOVER :
655661 description : |
656662 Enable re-synthesis for area reclaim.
@@ -693,12 +699,14 @@ CTS_CLUSTER_DIAMETER:
693699 default : 20
694700 stages :
695701 - cts
702+ tunable : 1
696703CTS_CLUSTER_SIZE :
697704 description : >
698705 Maximum number of sinks per cluster.
699706 default : 50
700707 stages :
701708 - cts
709+ tunable : 1
702710CTS_SNAPSHOT :
703711 description : |
704712 Creates ODB/SDC files prior to clock net and setup/hold repair.
Original file line number Diff line number Diff line change @@ -10,3 +10,4 @@ protobuf==3.20.3
1010SQLAlchemy == 1.4.17
1111urllib3 <= 1.26.15
1212matplotlib == 3.10.0
13+ pyyaml == 6.0.1
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