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jeffng-orjeffng-or
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Created separate SDCs for 0.2 and 0.15 PDKs
Signed-off-by: Jeff Ng <[email protected]>
1 parent 101da72 commit 14d97ea

26 files changed

+196
-29
lines changed

‎flow/designs/rapidus2hp/cva6/config.mk‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,11 @@ export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x128m2b1w0c1p0d0
8989
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
9090
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib
9191

92-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
92+
ifeq ($(RAPIDUS_PDK_VERSION),)
93+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_ps.sdc
94+
else
95+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
96+
endif
9397

9498
# Must be defined before the ifeq's
9599
export SYNTH_HDL_FRONTEND = slang

‎flow/designs/rapidus2hp/cva6/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
set clk_name main_clk
44
set clk_port clk_i
55
set clk_ports_list [list $clk_port]
6-
set clk_period 1125
6+
set clk_period 1.125
77
set input_delay 0.46
88
set output_delay 0.11
99
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

flow/designs/rapidus2hp/cva6/constraint_demo.sdc renamed to flow/designs/rapidus2hp/cva6/constraint_ps.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
set clk_name main_clk
44
set clk_port clk_i
55
set clk_ports_list [list $clk_port]
6-
set clk_period 1380
6+
set clk_period 1125
77
set input_delay 0.46
88
set output_delay 0.11
99
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

‎flow/designs/rapidus2hp/cva6/opt_constraint.sdc‎

Lines changed: 0 additions & 9 deletions
This file was deleted.

‎flow/designs/rapidus2hp/ethmac/config.mk‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,12 @@ export PLATFORM = rapidus2hp
33
export DESIGN_NAME = ethmac
44

55
export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/*.v))
6-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
6+
7+
ifeq ($(RAPIDUS_PDK_VERSION),)
8+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint_ps.sdc
9+
else
10+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
11+
endif
712
export ABC_AREA = 1
813

914
export CORE_UTILIZATION = 70

‎flow/designs/rapidus2hp/ethmac/constraint.sdc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
set top_clk_name wb_clk_i
2-
set clk_period 875
2+
set clk_period 0.875
33
set clk_io_pct 0.2
44
set clk_port [get_ports $top_clk_name]
55
create_clock -name $top_clk_name -period $clk_period $clk_port
@@ -11,7 +11,7 @@ set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \
1111

1212
set tx_clk_name mtx_clk_pad_i
1313
set tx_clk_port [get_ports $tx_clk_name]
14-
set tx_clk_period 300
14+
set tx_clk_period 0.300
1515
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
1616
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
1717
$tx_clk_port]
@@ -22,7 +22,7 @@ set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
2222

2323
set rx_clk_name mrx_clk_pad_i
2424
set rx_clk_port [get_ports $rx_clk_name]
25-
set rx_clk_period 110
25+
set rx_clk_period 0.110
2626
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
2727
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
2828
$rx_clk_port]

‎flow/designs/rapidus2hp/ethmac/constraint_ps.sdc‎

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
set top_clk_name wb_clk_i
2+
set clk_period 875
3+
set clk_io_pct 0.2
4+
set clk_port [get_ports $top_clk_name]
5+
create_clock -name $top_clk_name -period $clk_period $clk_port
6+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
7+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \
8+
$non_clock_inputs
9+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $top_clk_name \
10+
[all_outputs]
11+
12+
set tx_clk_name mtx_clk_pad_i
13+
set tx_clk_port [get_ports $tx_clk_name]
14+
set tx_clk_period 300
15+
create_clock -name $tx_clk_name -period $tx_clk_period $tx_clk_port
16+
set mtx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
17+
$tx_clk_port]
18+
set_input_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
19+
$mtx_non_clock_inputs
20+
set_output_delay [expr { $tx_clk_period * $clk_io_pct }] -clock $tx_clk_name \
21+
[all_outputs]
22+
23+
set rx_clk_name mrx_clk_pad_i
24+
set rx_clk_port [get_ports $rx_clk_name]
25+
set rx_clk_period 110
26+
create_clock -name $rx_clk_name -period $rx_clk_period $rx_clk_port
27+
set mrx_non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] \
28+
$rx_clk_port]
29+
set_input_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \
30+
$mrx_non_clock_inputs
31+
set_output_delay [expr { $rx_clk_period * $clk_io_pct }] -clock $rx_clk_name \
32+
[all_outputs]
33+
34+
set_clock_groups -name core_clock -logically_exclusive \
35+
-group [get_clocks $top_clk_name] \
36+
-group [get_clocks $tx_clk_name] \
37+
-group [get_clocks $rx_clk_name]
38+
39+
set_max_fanout 10 [current_design]

‎flow/designs/rapidus2hp/gcd/config.mk‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,12 @@ export DESIGN_NAME = gcd
33
export PLATFORM = rapidus2hp
44

55
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
6-
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
6+
7+
ifeq ($(RAPIDUS_PDK_VERSION),)
8+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_ps.sdc
9+
else
10+
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
11+
endif
712

813
export CORE_UTILIZATION = 45
914
export CORE_MARGIN = .5

‎flow/designs/rapidus2hp/gcd/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ current_design gcd
22

33
set clk_name core_clock
44
set clk_port_name clk
5-
set clk_period 100
5+
set clk_period 0.100
66
set clk_io_pct 0.2
77

88
set clk_port [get_ports $clk_port_name]

‎flow/designs/rapidus2hp/gcd/constraint_ps.sdc‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
current_design gcd
2+
3+
set clk_name core_clock
4+
set clk_port_name clk
5+
set clk_period 100
6+
set clk_io_pct 0.2
7+
8+
set clk_port [get_ports $clk_port_name]
9+
10+
create_clock -name $clk_name -period $clk_period $clk_port
11+
12+
set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
13+
14+
set_input_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
15+
$non_clock_inputs
16+
set_output_delay [expr { $clk_period * $clk_io_pct }] -clock $clk_name \
17+
[all_outputs]

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