For gf12/ca53 use a cached netlist to save time

This means no computing/checking for synth__design__instance__area__stdcell

Signed-off-by: Matt Liberty <[email protected]>

Author: maliberty

flow/designs/gf12/ca53/config.mk

@@ -1,10 +1,10 @@
 export DESIGN_NAME = ca53_cpu
 export PLATFORM    = gf12
 
-export SYNTH_HIERARCHICAL = 1
 export RTLMP_FLOW = True
 
-export VERILOG_FILES = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
+export VERILOG_FILES  = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
+export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
 
 export SDC_FILE      = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc