Mock array element latency (#1925)

* add target clock latency

Signed-off-by: Tom Spyrou <[email protected]>

* add source clock latency

Signed-off-by: Tom Spyrou <[email protected]>

* add element constraint.sdc, update metrics logs with paths used to pull the source latency numbers

Signed-off-by: Tom Spyrou <[email protected]>

* redirect report

Signed-off-by: Tom Spyrou <[email protected]>

* remove source latency accidentally added to top sdc

Signed-off-by: Tom Spyrou <[email protected]>

* set source latency to 0 before write_timing_model

Signed-off-by: Tom Spyrou <[email protected]>

* comments to show where latency should be added

Signed-off-by: Tom Spyrou <[email protected]>

* use reg to reg paths to find metrics for latency

Signed-off-by: Tom Spyrou <[email protected]>

* use reg to reg paths to find metrics for latency

Signed-off-by: Tom Spyrou <[email protected]>

* guard against no registers

Signed-off-by: Tom Spyrou <[email protected]>

---------

Signed-off-by: Tom Spyrou <[email protected]>
Co-authored-by: Tom Spyrou <[email protected]>

Author: tspyrou

flow/designs/asap7/mock-array/Element/constraints.sdc

@@ -14,11 +14,15 @@ set clk_port [get_ports $clk_port_name]
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
 set_clock_uncertainty -setup 20.0 [get_clocks $clk_name]
 set_clock_uncertainty -hold  20.0 [get_clocks $clk_name]
+# From top level run's metrics
+#set_clock_latency -source 350 [get_clocks $clk_name]
 
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name ${clk_name}_vir
 set_clock_uncertainty -setup 20.0 [get_clocks ${clk_name}_vir]
 set_clock_uncertainty -hold 20.0  [get_clocks ${clk_name}_vir]
 set_clock_latency 70 [get_clocks ${clk_name}_vir]
+# From top level run's metrics
+#set_clock_latency -source 380 [get_clocks ${clk_name}_vir]
 
 set_max_transition 250 [current_design]
 set_max_transition 100 -clock_path [all_clocks]

flow/designs/asap7/mock-array/constraints.sdc

@@ -13,7 +13,6 @@ set_clock_uncertainty 10 [get_clocks $clk_name]
 
 create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
 set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
-set_clock_latency     380 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
 
 set clk_port [get_ports $clk_port_name]
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

flow/scripts/generate_abstract.tcl

@@ -16,7 +16,8 @@ if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} {
 if {$design_stage >= 4} {
   set_propagated_clock [all_clocks]
 }
-
+# write_timing_model includes the source latency in the model
+set_clock_latency -source 0 [all_clocks]
 puts "Generating abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef

flow/scripts/report_metrics.tcl

@@ -152,6 +152,53 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
       set path_delay -1
       set path_slack 0
     }
+
+    if { [llength [all_registers]] != 0} {
+    report_puts "\n=========================================================================="
+    report_puts "$when report_checks -path_delay max reg to reg"
+    report_puts "--------------------------------------------------------------------------"
+    report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename    
+    report_puts "\n=========================================================================="
+    report_puts "$when report_checks -path_delay min reg to reg"
+    report_puts "--------------------------------------------------------------------------"
+    report_checks -path_delay min -from [all_registers] -to [all_registers]  -format full_clock_expanded >> $filename         
+
+    set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
+    if {$inp_to_reg_critical_path != ""} {
+      set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+    } else {
+      set target_clock_latency_max 0	
+    }
+
+
+    set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
+    if {$inp_to_reg_critical_path != ""} {
+      set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+      set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
+    } else {
+      set target_clock_latency_min 0	
+      set source_clock_latency 0
+    }
+      
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path target clock latency max path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$target_clock_latency_max"
+
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path target clock latency min path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$target_clock_latency_min"
+
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path source clock latency min path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$source_clock_latency"
+    } else {
+    puts "No registers in design"
+    }
+    # end if all_registers
+      
     report_puts "\n=========================================================================="
     report_puts "$when critical path delay"
     report_puts "--------------------------------------------------------------------------"