added DFF_MAP_FILE flow variable to map DFF's

tclfmt fixes

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

docs/user/FlowVariables.md

@@ -128,6 +128,7 @@ configuration file.
 | <a name="DETAILED_ROUTE_ARGS"></a>DETAILED_ROUTE_ARGS| Add additional arguments for debugging purposes during detail route.| |
 | <a name="DETAILED_ROUTE_END_ITERATION"></a>DETAILED_ROUTE_END_ITERATION| Maximum number of iterations.| 64|
 | <a name="DFF_LIB_FILES"></a>DFF_LIB_FILES| Technology mapping liberty files for flip-flops.| |
+| <a name="DFF_MAP_FILE"></a>DFF_MAP_FILE| List of D flip flops treated as a black box by Yosys.| |
 | <a name="DIE_AREA"></a>DIE_AREA| The die area specified as a list of lower-left and upper-right corners in microns (X1 Y1 X2 Y2).| |
 | <a name="DONT_BUFFER_PORTS"></a>DONT_BUFFER_PORTS| Do not buffer input/output ports during floorplanning.| 0|
 | <a name="DONT_USE_CELLS"></a>DONT_USE_CELLS| Dont use cells eases pin access in detailed routing.| |
@@ -276,6 +277,7 @@ configuration file.
 - [ABC_LOAD_IN_FF](#ABC_LOAD_IN_FF)
 - [ADDER_MAP_FILE](#ADDER_MAP_FILE)
 - [CLKGATE_MAP_FILE](#CLKGATE_MAP_FILE)
+- [DFF_MAP_FILE](#DFF_MAP_FILE)
 - [LATCH_MAP_FILE](#LATCH_MAP_FILE)
 - [MIN_BUF_CELL_AND_PORTS](#MIN_BUF_CELL_AND_PORTS)
 - [SDC_FILE](#SDC_FILE)

flow/scripts/synth.tcl

@@ -1,3 +1,36 @@
+#
+# Extracts and returns module names from Verilog file
+#
+proc get_module_names { file_path } {
+  set module_list [list]
+  if { [catch { set fid [open $file_path r] } err] } {
+    error "Failed to open file $file_path: $err"
+  }
+
+  set regex {^[ \t]*module[ \t]+([A-Za-z_$][A-Za-z0-9_$]*)}
+
+  while { [gets $fid line] >= 0 } {
+    if { [regexp -nocase $regex $line match_all module_name] } {
+      lappend module_list $module_name
+    }
+  }
+
+  close $fid
+  return $module_list
+}
+
+#
+# Builds dfflegalize arg list
+#
+proc get_dfflegalize_args { file_path } {
+  set legalize_args [list]
+  set module_names [get_module_names $file_path]
+  foreach module_name $module_names {
+    lappend legalize_args -cell $module_name x
+  }
+  return $legalize_args
+}
+
 source $::env(SCRIPTS_DIR)/synth_preamble.tcl
 read_checkpoint $::env(RESULTS_DIR)/1_1_yosys_canonicalize.rtlil
 
@@ -143,6 +176,10 @@ if { [env_var_exists_and_non_empty LATCH_MAP_FILE] } {
 # dfflibmap only supports one liberty file
 if { [env_var_exists_and_non_empty DFF_LIB_FILE] } {
   dfflibmap -liberty $::env(DFF_LIB_FILE) {*}$lib_dont_use_args
+} elseif { [env_var_exists_and_non_empty DFF_MAP_FILE] } {
+  set legalize_args [get_dfflegalize_args $::env(DFF_MAP_FILE)]
+  dfflegalize {*}$legalize_args
+  techmap -map $::env(DFF_MAP_FILE)
 } else {
   dfflibmap {*}$lib_args {*}$lib_dont_use_args
 }

flow/scripts/variables.yaml

@@ -292,6 +292,11 @@ SYNTH_RETIME_MODULES:
     optimal distribution of registers on long pipelines. See OR discussion #8080.
   stages:
     - synth
+DFF_MAP_FILE:
+  description: |
+    List of D flip flops treated as a black box by Yosys.
+  stages:
+    - synth
 LATCH_MAP_FILE:
   description: |
     List of latches treated as a black box by Yosys.