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lines changed Original file line number Diff line number Diff line change @@ -337,13 +337,28 @@ CTS_ARGS:
337337HOLD_SLACK_MARGIN :
338338 description : >
339339 Specifies a time margin for the slack when fixing hold violations.
340- This option allows you to overfix.
340+ This option allows you to overfix or underfix(negative value, terminate
341+ retiming before 0 or positive slack).
342+ stages :
343+ - cts
344+ - floorplan
345+ - grt
341346SETUP_SLACK_MARGIN :
342347 description : >
343348 Specifies a time margin for the slack when fixing setup violations.
349+ This option allows you to overfix or underfix(negative value, terminate
350+ retiming before 0 or positive slack).
351+ stages :
352+ - cts
353+ - floorplan
354+ - grt
344355SKIP_GATE_CLONING :
345356 description : >
346357 Do not use gate cloning transform to fix timing violations (default: use gate cloning).
358+ stages :
359+ - cts
360+ - floorplan
361+ - grt
347362SKIP_LAST_GASP :
348363 description : >
349364 Do not use last gasp optimization to fix timing violations (default: use gate last gasp).
@@ -354,6 +369,10 @@ SKIP_LAST_GASP:
354369SKIP_PIN_SWAP :
355370 description : >
356371 Do not use pin swapping as a transform to fix timing violations (default: use pin swapping).
372+ stages :
373+ - cts
374+ - floorplan
375+ - grt
357376REMOVE_CELLS_FOR_EQY :
358377 description : >
359378 String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.
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