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Merge branch 'master' into mb@update
Signed-off-by: louiic <[email protected]>
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‎docs/user/FlowVariables.md‎

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@@ -77,8 +77,8 @@ Note:
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| Clock Tree Synthesis | | | | | |
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| `CTS_BUF_CELL` | = | = | = | = | = |
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| `CTS_BUF_DISTANCE` | N/A | N/A | N/A | = | = |
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| `ENABLE_GATE_CLONING` | ?= | ?= | ?= | ?= | ?= |
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| `FILL_CELLS` | = | = | = | = | = |
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| `SKIP_GATE_CLONING` | ?= | ?= | ?= | ?= | ?= |
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| `SKIP_PIN_SWAP` | ?= | ?= | ?= | ?= | ?= |
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| `TNS_END_PERCENT` | ?= | ?= | | ?= | ?= |
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| Routing | | | | | |
@@ -88,6 +88,7 @@ Note:
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| `MAX_ROUTING_LAYER` | = | = | = | = | ?= |
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| `MIN_ROUTING_LAYER` | = | = | = | = | ?= |
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| `RCX_RULES` | = | = | = | = | = |
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| `RECOVER_POWER` | ?= | ?= | ?= | ?= | ?= |
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### Library Setup
@@ -169,10 +170,10 @@ Note:
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| Variable | Description |
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|-----------------------|--------------------------------------------------------------------------------------------------------------|
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| `CTS_BUF_CELL` | The buffer cell used in the clock tree. |
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| `ENABLE_GATE_CLONING` | Use gate cloning transform to fix timing violations when appropriate (default: do not use cloning) |
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| `FILL_CELLS` | Fill cells are used to fill empty sites. |
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| `HOLD_SLACK_MARGIN` | Specifies a time margin for the slack when fixing hold violations. This option allow you to overfix. |
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| `SETUP_SLACK_MARGIN` | Specifies a time margin for the slack when fixing setup violations. |
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| `SKIP_GATE_CLONING` | Do not use gate cloning transform to fix timing violations (default: use gate cloning) |
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| `SKIP_PIN_SWAP` | Do not use pin swapping as a transform to fix timing violations (default: use pin swapping) |
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| `TNS_END_PERCENT` | Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed |
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@@ -181,11 +182,12 @@ Note:
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| Variable | Description |
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|-----------------------|-------------------------------------------------------------------------|
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| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
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| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
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| `DETAILED_ROUTE_ARGS` | Add additional arguments for debugging purpose during detail route. |
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| `MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros.|
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|-----------------------|---------------------------------------------------------------------------------------------------|
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| `MIN_ROUTING_LAYER` | The lowest metal layer name to be used in routing. |
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| `MAX_ROUTING_LAYER` | The highest metal layer name to be used in routing. |
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| `DETAILED_ROUTE_ARGS` | Add additional arguments for debugging purpose during detail route. |
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| `MACRO_EXTENSION` | Sets the number of GCells added to the blockages boundaries from macros. |
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| `RECOVER_POWER` | Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100]. |
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### Extraction

‎flow/designs/asap7/aes_lvt/config.mk‎

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export PLATFORM = asap7
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export DESIGN_NAME = aes_cipher_top
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export DESIGN_NICKNAME = aes_lvt
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export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export ABC_AREA = 1
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export CORE_UTILIZATION = 40
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY = 0.65
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export TNS_END_PERCENT = 100
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export ASAP7_USELVT = 1
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/asap7sc7p5t_AO_RVT_FF_nldm_211120.lib.gz \
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$(PLATFORM_DIR)/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz \
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$(PLATFORM_DIR)/lib/asap7sc7p5t_OA_RVT_FF_nldm_211120.lib.gz \
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$(PLATFORM_DIR)/lib/asap7sc7p5t_SIMPLE_RVT_FF_nldm_211120.lib.gz \
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$(PLATFORM_DIR)/lib/asap7sc7p5t_SEQ_RVT_FF_nldm_220123.lib
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export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/asap7sc7p5t_28_R_220121a.gds
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/asap7sc7p5t_28_R_1x_220121a.lef
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export RECOVER_POWER = 20

‎flow/designs/asap7/aes_lvt/constraint.sdc‎

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set clk_name clk
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set clk_port_name clk
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set clk_period 400
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
11+
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]

‎flow/designs/asap7/aes_lvt/metadata-base-ok.json‎

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}

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