Merge pull request #2399 from Pinata-Consulting/scripts-cleanup-5

scripts: more cleanup

Author: maliberty

flow/scripts/detail_place.tcl

@@ -16,7 +16,7 @@ proc do_dpl {} {
   detailed_placement
 
   if {[env_var_equals ENABLE_DPO 1]} {
-    if {[info exist ::env(DPO_MAX_DISPLACEMENT)]} {
+    if {[env_var_exists_and_non_empty DPO_MAX_DISPLACEMENT]} {
       improve_placement -max_displacement $::env(DPO_MAX_DISPLACEMENT)
     } else {
       improve_placement

flow/scripts/detail_route.tcl

@@ -50,7 +50,7 @@ set_global_routing_layer_adjustment $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAY
 set_routing_layers -signal $env(MIN_ROUTING_LAYER)-$env(MAX_ROUTING_LAYER)
 
 
-if {![info exist ::env(SKIP_ANTENNA_REPAIR_POST_DRT)]} {
+if {![env_var_equals SKIP_ANTENNA_REPAIR_POST_DRT 1]} {
   set repair_antennas_iters 1
   repair_antennas
   while {[check_antennas] && $repair_antennas_iters < 5} {

flow/scripts/final_report.tcl

@@ -17,11 +17,11 @@ write_def $::env(RESULTS_DIR)/6_final.def
 write_verilog $::env(RESULTS_DIR)/6_final.v
 
 # Run extraction and STA
-if {[info exist ::env(RCX_RULES)]} {
+if {[env_var_exists_and_non_empty RCX_RULES]} {
 
   # Set RC corner for RCX
   # Set in config.mk
-  if {[info exist ::env(RCX_RC_CORNER)]} {
+  if {[env_var_exists_and_non_empty RCX_RC_CORNER]} {
     set rc_corner $::env(RCX_RC_CORNER)
   }
 
@@ -37,7 +37,7 @@ if {[info exist ::env(RCX_RULES)]} {
   read_spef $::env(RESULTS_DIR)/6_final.spef
 
   # Static IR drop analysis
-  if {[info exist ::env(PWR_NETS_VOLTAGES)] && [string length $::env(PWR_NETS_VOLTAGES)] > 0} {
+  if {[env_var_exists_and_non_empty PWR_NETS_VOLTAGES]} {
     dict for {pwrNetName pwrNetVoltage}  {*}$::env(PWR_NETS_VOLTAGES) {
         set_pdnsim_net_voltage -net ${pwrNetName} -voltage ${pwrNetVoltage}
         analyze_power_grid -net ${pwrNetName} \
@@ -46,7 +46,7 @@ if {[info exist ::env(RCX_RULES)]} {
   } else {
     puts "IR drop analysis for power nets is skipped because PWR_NETS_VOLTAGES is undefined"
   }
-  if {[info exist ::env(GND_NETS_VOLTAGES)] && [string length $::env(GND_NETS_VOLTAGES)] > 0} {
+  if {[env_var_exists_and_non_empty GND_NETS_VOLTAGES]} {
     dict for {gndNetName gndNetVoltage}  {*}$::env(GND_NETS_VOLTAGES) {
         set_pdnsim_net_voltage -net ${gndNetName} -voltage ${gndNetVoltage}
         analyze_power_grid -net ${gndNetName} \

flow/scripts/generate_abstract.tcl

@@ -24,7 +24,7 @@ puts "Generating abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef
 
-if {[info exist ::env(CDL_FILES)]} {
+if {[env_var_exists_and_non_empty CDL_FILES]} {
   cdl read_masters $::env(CDL_FILES)
   cdl out $::env(RESULTS_DIR)/$stem.cdl
 }

flow/scripts/global_place.tcl

@@ -41,7 +41,7 @@ if {$result != 0} {
 
 estimate_parasitics -placement
 
-if {[info exist ::env(CLUSTER_FLOPS)]} {
+if {[env_var_equals CLUSTER_FLOPS 1]} {
   cluster_flops
   estimate_parasitics -placement
 }

flow/scripts/global_route.tcl

@@ -6,7 +6,7 @@ proc global_route_helper {} {
   source $::env(SCRIPTS_DIR)/load.tcl
   load_design 4_cts.odb 4_cts.sdc
 
-  if {[info exist ::env(PRE_GLOBAL_ROUTE)]} {
+  if {[env_var_exists_and_non_empty PRE_GLOBAL_ROUTE]} {
     source $::env(PRE_GLOBAL_ROUTE)
   }
 
@@ -45,7 +45,7 @@ proc global_route_helper {} {
   set_propagated_clock [all_clocks]
   estimate_parasitics -global_routing
 
-  if {[info exist ::env(DONT_USE_CELLS)]} {
+  if {[env_var_exists_and_non_empty DONT_USE_CELLS]} {
     set_dont_use $::env(DONT_USE_CELLS)
   }
 
@@ -88,7 +88,7 @@ proc global_route_helper {} {
 
   recover_power
 
-  if {![info exist ::env(SKIP_ANTENNA_REPAIR)]} {
+  if {![env_var_equals SKIP_ANTENNA_REPAIR 1]} {
     puts "Repair antennas..."
     repair_antennas -iterations 5
     check_placement -verbose