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Tighten up Rapidus designs after setting cell padding to 0
Signed-off-by: Jeff Ng <[email protected]>
1 parent 9fc811c commit 1ceeae7

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12 files changed

+58
-51
lines changed

12 files changed

+58
-51
lines changed

‎flow/designs/rapidus2hp/cva6/config.mk‎

Lines changed: 5 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -64,8 +64,8 @@ export VERILOG_FILES = $(sort $(wildcard $(SRC_HOME)/common/local/util/
6464
$(SRC_HOME)/core/cvxif_example/include/cvxif_instr_pkg.sv \
6565
$(sort $(wildcard $(SRC_HOME)/core/frontend/*.sv)) \
6666
$(SRC_HOME)/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv \
67-
$(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim.sv \
68-
$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
67+
$(PLATFORM_DIR)/ram/verilog/fakeram7_64x256_shim_half.sv \
68+
$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
6969
$(PLATFORM_DIR)/ram/verilog/fakeram7_128x64_shim.sv \
7070
$(PLATFORM_DIR)/ram/verilog/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.sv \
7171
$(PLATFORM_DIR)/ram/verilog/fakeram7_64x28_shim.sv \
@@ -79,12 +79,12 @@ export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/core/include
7979

8080
export VERILOG_DEFINES += -D HPDCACHE_ASSERT_OFF
8181

82-
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
82+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
8383
$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
8484
$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef \
8585
$(PLATFORM_DIR)/ram/lef/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lef
8686

87-
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x256m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
87+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x128m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
8888
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p128x64m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
8989
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x28m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib \
9090
$(PLATFORM_DIR)/ram/lib/sacrls0g0d1p64x25m2b1w0c1p0d0i0s0cr0rr0rm4rw00ms0.lib
@@ -95,20 +95,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constr
9595
export SYNTH_HDL_FRONTEND = slang
9696
export SYNTH_HIERARCHICAL = 1
9797

98-
ifeq ($(SYNTH_HDL_FRONTEND),verific)
99-
# Reduce utilization for verific since it runs into issues with DPL not being
100-
# able to place instances or with one-site gap/overlap issues
101-
export CORE_UTILIZATION = 45
102-
else
103-
# Reduce the amount of resizing done between GPL and DPL
104-
export EARLY_SIZING_CAP_RATIO = 6
105-
ifeq ($(PLACE_SITE),SC6T)
106-
# Decrease the utilization so that the tall macros fit
107-
export CORE_UTILIZATION = 50
108-
else
109-
export CORE_UTILIZATION = 55
110-
endif
111-
endif
98+
export CORE_UTILIZATION = 65
11299

113100
export CORE_MARGIN = 2
114101
export MACRO_PLACE_HALO = 2 2

‎flow/designs/rapidus2hp/cva6/constraint.sdc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
set clk_name main_clk
44
set clk_port clk_i
55
set clk_ports_list [list $clk_port]
6-
set clk_period 1200
6+
set clk_period 1125
77
set input_delay 0.46
88
set output_delay 0.11
99
create_clock [get_ports $clk_port] -name $clk_name -period $clk_period

‎flow/designs/rapidus2hp/ethmac/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/$(DESIGN_NIC
66
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
77
export ABC_AREA = 1
88

9-
export CORE_UTILIZATION = 45
9+
export CORE_UTILIZATION = 70
1010
export CORE_ASPECT_RATIO = 1
1111
export CORE_MARGIN = 0.75
1212
export PLACE_DENSITY = 0.70

‎flow/designs/rapidus2hp/ethmac/rules-base.json‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,54 +1,54 @@
11
{
22
"synth__design__instance__area__stdcell": {
3-
"value": 3307.96,
3+
"value": 3301.52,
44
"compare": "<="
55
},
66
"constraints__clocks__count": {
77
"value": 3,
88
"compare": "=="
99
},
1010
"placeopt__design__instance__area": {
11-
"value": 3774,
11+
"value": 3426,
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
15-
"value": 70864,
15+
"value": 68252,
1616
"compare": "<="
1717
},
1818
"detailedplace__design__violations": {
1919
"value": 0,
2020
"compare": "=="
2121
},
2222
"cts__design__instance__count__setup_buffer": {
23-
"value": 6162,
23+
"value": 5935,
2424
"compare": "<="
2525
},
2626
"cts__design__instance__count__hold_buffer": {
27-
"value": 6162,
27+
"value": 5935,
2828
"compare": "<="
2929
},
3030
"globalroute__antenna_diodes_count": {
3131
"value": 0,
3232
"compare": "<="
3333
},
3434
"finish__timing__setup__ws": {
35-
"value": -77.13,
35+
"value": -67.35,
3636
"compare": ">="
3737
},
3838
"finish__design__instance__area": {
39-
"value": 3961,
39+
"value": 3622,
4040
"compare": "<="
4141
},
4242
"finish__timing__drv__setup_violation_count": {
43-
"value": 3081,
43+
"value": 2968,
4444
"compare": "<="
4545
},
4646
"finish__timing__drv__hold_violation_count": {
4747
"value": 100,
4848
"compare": "<="
4949
},
5050
"finish__timing__wns_percent_delay": {
51-
"value": -51.34,
51+
"value": -47.89,
5252
"compare": ">="
5353
}
5454
}

‎flow/designs/rapidus2hp/gcd/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,6 @@ export PLATFORM = rapidus2hp
55
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/gcd.v
66
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
77

8-
export CORE_UTILIZATION = 30
9-
export CORE_MARGIN = .75
8+
export CORE_UTILIZATION = 45
9+
export CORE_MARGIN = .5
1010
export PLACE_DENSITY = 0.42

‎flow/designs/rapidus2hp/gcd/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
15-
"value": 738,
15+
"value": 696,
1616
"compare": "<="
1717
},
1818
"detailedplace__design__violations": {
@@ -32,7 +32,7 @@
3232
"compare": "<="
3333
},
3434
"finish__timing__setup__ws": {
35-
"value": -45.18,
35+
"value": -43.47,
3636
"compare": ">="
3737
},
3838
"finish__design__instance__area": {

‎flow/designs/rapidus2hp/hercules_idecode/rules-base.json‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
"compare": "=="
99
},
1010
"placeopt__design__instance__area": {
11-
"value": 12586,
11+
"value": 12567,
1212
"compare": "<="
1313
},
1414
"placeopt__design__instance__count__stdcell": {
@@ -30,5 +30,25 @@
3030
"globalroute__antenna_diodes_count": {
3131
"value": 0,
3232
"compare": "<="
33+
},
34+
"finish__timing__setup__ws": {
35+
"value": -302.33,
36+
"compare": ">="
37+
},
38+
"finish__design__instance__area": {
39+
"value": 12842,
40+
"compare": "<="
41+
},
42+
"finish__timing__drv__setup_violation_count": {
43+
"value": 13929,
44+
"compare": "<="
45+
},
46+
"finish__timing__drv__hold_violation_count": {
47+
"value": 100,
48+
"compare": "<="
49+
},
50+
"finish__timing__wns_percent_delay": {
51+
"value": -62.29,
52+
"compare": ">="
3353
}
3454
}

‎flow/designs/rapidus2hp/hercules_is_int/rules-base.json‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,23 +32,23 @@
3232
"compare": "<="
3333
},
3434
"finish__timing__setup__ws": {
35-
"value": -510.05,
35+
"value": -408.98,
3636
"compare": ">="
3737
},
3838
"finish__design__instance__area": {
39-
"value": 35330,
39+
"value": 35285,
4040
"compare": "<="
4141
},
4242
"finish__timing__drv__setup_violation_count": {
4343
"value": 32486,
4444
"compare": "<="
4545
},
4646
"finish__timing__drv__hold_violation_count": {
47-
"value": 110,
47+
"value": 102,
4848
"compare": "<="
4949
},
5050
"finish__timing__wns_percent_delay": {
51-
"value": -65.28,
51+
"value": -61.95,
5252
"compare": ">="
5353
}
5454
}

‎flow/designs/rapidus2hp/ibex/config.mk‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ else
1919
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
2020
endif
2121

22-
export CORE_UTILIZATION = 45
22+
export CORE_UTILIZATION = 70
2323
export CORE_ASPECT_RATIO = 1
2424
export CORE_MARGIN = 0.75
2525
export PLACE_DENSITY_LB_ADDON = 0.20

‎flow/designs/rapidus2hp/ibex/rules-base.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,15 @@
3232
"compare": "<="
3333
},
3434
"finish__timing__setup__ws": {
35-
"value": -134.19,
35+
"value": -119.54,
3636
"compare": ">="
3737
},
3838
"finish__design__instance__area": {
3939
"value": 1105,
4040
"compare": "<="
4141
},
4242
"finish__timing__drv__setup_violation_count": {
43-
"value": 1572,
43+
"value": 885,
4444
"compare": "<="
4545
},
4646
"finish__timing__drv__hold_violation_count": {

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