Merge remote-tracking branch 'private/master' into secure-gpl-extend-iter-by-routability

Author: gudeh

docs/user/FlowVariables.md

@@ -238,7 +238,7 @@ configuration file.
 | <a name="TECH_LEF"></a>TECH_LEF| A technology LEF file of the PDK that includes all relevant information regarding metal layers, vias, and spacing requirements.| |
 | <a name="TIEHI_CELL_AND_PORT"></a>TIEHI_CELL_AND_PORT| Tie high cells used in Yosys synthesis to replace a logical 1 in the Netlist.| |
 | <a name="TIELO_CELL_AND_PORT"></a>TIELO_CELL_AND_PORT| Tie low cells used in Yosys synthesis to replace a logical 0 in the Netlist.| |
-| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| |
+| <a name="TIE_SEPARATION"></a>TIE_SEPARATION| Distance separating tie high/low instances from the load.| 0|
 | <a name="TNS_END_PERCENT"></a>TNS_END_PERCENT| Default TNS_END_PERCENT value for post CTS timing repair. Try fixing all violating endpoints by default (reduce to 5% for runtime). Specifies how many percent of violating paths to fix [0-100]. Worst path will always be fixed.| 100|
 | <a name="USE_FILL"></a>USE_FILL| Whether to perform metal density filling.| 0|
 | <a name="VERILOG_DEFINES"></a>VERILOG_DEFINES| Preprocessor defines passed to the language frontend. Example: `-D HPDCACHE_ASSERT_OFF`| |
@@ -331,6 +331,7 @@ configuration file.
 - [TAPCELL_TCL](#TAPCELL_TCL)
 - [TIEHI_CELL_AND_PORT](#TIEHI_CELL_AND_PORT)
 - [TIELO_CELL_AND_PORT](#TIELO_CELL_AND_PORT)
+- [TIE_SEPARATION](#TIE_SEPARATION)
 - [TNS_END_PERCENT](#TNS_END_PERCENT)
 
 ## place variables
@@ -353,7 +354,6 @@ configuration file.
 - [ROUTING_LAYER_ADJUSTMENT](#ROUTING_LAYER_ADJUSTMENT)
 - [SKIP_REPORT_METRICS](#SKIP_REPORT_METRICS)
 - [SWAP_ARITH_OPERATORS](#SWAP_ARITH_OPERATORS)
-- [TIE_SEPARATION](#TIE_SEPARATION)
 
 ## cts variables
 

flow/designs/nangate45/gcd/config.mk

@@ -12,3 +12,6 @@ export CORE_UTILIZATION ?= 55
 export PLACE_DENSITY_LB_ADDON = 0.20
 export TNS_END_PERCENT        = 100
 export REMOVE_CELLS_FOR_EQY   = TAPCELL*
+
+# This needs a smaller pitch to accomodate a small block
+export PDN_TCL ?= $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/grid_strategy-M1-M4-M7.tcl

flow/designs/nangate45/gcd/grid_strategy-M1-M4-M7.tcl

@@ -0,0 +1,22 @@
+####################################
+# global connections
+####################################
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDD$} -power
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDPE$}
+add_global_connection -net {VDD} -inst_pattern {.*} -pin_pattern {^VDDCE$}
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSS$} -ground
+add_global_connection -net {VSS} -inst_pattern {.*} -pin_pattern {^VSSE$}
+global_connect
+####################################
+# voltage domains
+####################################
+set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
+####################################
+# standard cell grid
+####################################
+define_pdn_grid -name {grid} -voltage_domains {CORE}
+add_pdn_stripe -grid {grid} -layer {metal1} -width {0.17} -pitch {2.4} -offset {0} -followpins
+add_pdn_stripe -grid {grid} -layer {metal4} -width {0.48} -pitch {28.0} -offset {2}
+add_pdn_stripe -grid {grid} -layer {metal7} -width {1.40} -pitch {15.0} -offset {2}
+add_pdn_connect -grid {grid} -layers {metal1 metal4}
+add_pdn_connect -grid {grid} -layers {metal4 metal7}

flow/scripts/floorplan.tcl

@@ -97,7 +97,19 @@ source_env_var_if_exists FOOTPRINT_TCL
 
 # This needs to come before any call to remove_buffers.  You could have one
 # tie driving multiple buffers that drive multiple outputs.
-repair_tie_fanout_helper
+# Repair tie lo fanout
+puts "Repair tie lo fanout..."
+set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
+set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
+set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
+repair_tie_fanout -separation $::env(TIE_SEPARATION) $tielo_pin
+
+# Repair tie hi fanout
+puts "Repair tie hi fanout..."
+set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
+set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
+set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
+repair_tie_fanout -separation $::env(TIE_SEPARATION) $tiehi_pin
 
 if { [env_var_exists_and_non_empty SWAP_ARITH_OPERATORS] } {
   estimate_parasitics -placement

flow/scripts/global_place.tcl

@@ -18,7 +18,14 @@ if { ![env_var_exists_and_non_empty FOOTPRINT] } {
   }
 }
 
-fast_route
+if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
+  log_cmd source $::env(FASTROUTE_TCL)
+} else {
+  log_cmd \
+    set_global_routing_layer_adjustment \
+    $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT)
+  log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
+}
 
 set global_placement_args {}
 

flow/scripts/util.tcl

@@ -13,39 +13,6 @@ proc log_cmd { cmd args } {
   return $result
 }
 
-proc repair_tie_fanout_helper { } {
-  if { [env_var_exists_and_non_empty TIE_SEPARATION] } {
-    set tie_separation $env(TIE_SEPARATION)
-  } else {
-    set tie_separation 0
-  }
-
-  # Repair tie lo fanout
-  puts "Repair tie lo fanout..."
-  set tielo_cell_name [lindex $::env(TIELO_CELL_AND_PORT) 0]
-  set tielo_lib_name [get_name [get_property [lindex [get_lib_cell $tielo_cell_name] 0] library]]
-  set tielo_pin $tielo_lib_name/$tielo_cell_name/[lindex $::env(TIELO_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $tie_separation $tielo_pin
-
-  # Repair tie hi fanout
-  puts "Repair tie hi fanout..."
-  set tiehi_cell_name [lindex $::env(TIEHI_CELL_AND_PORT) 0]
-  set tiehi_lib_name [get_name [get_property [lindex [get_lib_cell $tiehi_cell_name] 0] library]]
-  set tiehi_pin $tiehi_lib_name/$tiehi_cell_name/[lindex $::env(TIEHI_CELL_AND_PORT) 1]
-  repair_tie_fanout -separation $tie_separation $tiehi_pin
-}
-
-proc fast_route { } {
-  if { [env_var_exists_and_non_empty FASTROUTE_TCL] } {
-    log_cmd source $::env(FASTROUTE_TCL)
-  } else {
-    log_cmd \
-      set_global_routing_layer_adjustment \
-      $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) $::env(ROUTING_LAYER_ADJUSTMENT)
-    log_cmd set_routing_layers -signal $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER)
-  }
-}
-
 proc repair_timing_helper { args } {
   set additional_args "$args -verbose"
   append_env_var additional_args SETUP_SLACK_MARGIN -setup_margin 1

flow/scripts/variables.yaml

@@ -232,7 +232,8 @@ TIE_SEPARATION:
   description: |
     Distance separating tie high/low instances from the load.
   stages:
-    - place
+    - floorplan
+  default: 0
 EARLY_SIZING_CAP_RATIO:
   description: |
     Ratio between the input pin capacitance and the output pin load during initial gate sizing.

flow/test/test_helper.sh

@@ -8,9 +8,10 @@ cd "$(dirname "$(readlink -f "$0")")/../"
 DESIGN_NAME=${1:-gcd}
 PLATFORM=${2:-nangate45}
 CONFIG_MK=${3:-config.mk}
-if [ $# -eq 4 ]; then
+if [ $# -ge 4 ]; then
   FLOW_VARIANT=$4
 fi
+TARGET=${5:-'finish metadata'}
 DESIGN_CONFIG=./designs/$PLATFORM/$DESIGN_NAME/$CONFIG_MK
 LOG_FILE=./logs/$PLATFORM/$DESIGN_NAME.log
 mkdir -p "./logs/$PLATFORM"
@@ -26,12 +27,16 @@ $__make clean_all clean_metadata 2>&1 | tee "$LOG_FILE"
 # turn off abort on error so we can always capture the result
 set +e
 
-$__make finish metadata 2>&1 | tee -a "$LOG_FILE"
+eval $__make "${TARGET}" 2>&1 | tee -a "$LOG_FILE"
 
 # Save the return code to return as the overall status after we package
 # the results
 ret=$?
 
+if [ "${TARGET}" != "finish metadata" ]; then
+  exit $ret
+fi
+
 if [ -z "${PRIVATE_DIR+x}" ]; then
   PRIVATE_DIR="../../private_tool_scripts"
 fi