Added LAYER_PARASITICS_FILE flow variable for setRC.tcl

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

docs/user/FlowVariables.md

@@ -159,6 +159,7 @@ configuration file.
 | <a name="IR_DROP_LAYER"></a>IR_DROP_LAYER| Default metal layer to report IR drop.| |
 | <a name="KLAYOUT_TECH_FILE"></a>KLAYOUT_TECH_FILE| A mapping from LEF/DEF to GDS using the KLayout tool.| |
 | <a name="LATCH_MAP_FILE"></a>LATCH_MAP_FILE| Optional mapping file supplied to Yosys to map latches| |
+| <a name="LAYER_PARASITICS_FILE"></a>LAYER_PARASITICS_FILE| Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.| |
 | <a name="LIB_FILES"></a>LIB_FILES| A Liberty file of the standard cell library with PVT characterization, input and output characteristics, timing and power definitions for each cell.| |
 | <a name="MACRO_BLOCKAGE_HALO"></a>MACRO_BLOCKAGE_HALO| Distance beyond the edges of a macro that will also be covered by the blockage generated for that macro. Note that the default macro blockage halo comes from the largest of the specified MACRO_PLACE_HALO x or y values. This variable overrides that calculation.| |
 | <a name="MACRO_EXTENSION"></a>MACRO_EXTENSION| Sets the number of GCells added to the blockages boundaries from macros.| |
@@ -518,6 +519,7 @@ configuration file.
 - [GUI_TIMING](#GUI_TIMING)
 - [IR_DROP_LAYER](#IR_DROP_LAYER)
 - [KLAYOUT_TECH_FILE](#KLAYOUT_TECH_FILE)
+- [LAYER_PARASITICS_FILE](#LAYER_PARASITICS_FILE)
 - [LIB_FILES](#LIB_FILES)
 - [MACRO_EXTENSION](#MACRO_EXTENSION)
 - [PLATFORM](#PLATFORM)

flow/scripts/floorplan_to_place.tcl

@@ -321,7 +321,11 @@ write_db $::env(RESULTS_DIR)/3_4_place_resized.odb
 # Detailed placement
 utl::set_metrics_stage "detailedplace__{}"
 
-source $::env(PLATFORM_DIR)/setRC.tcl
+if { [env_var_exists_and_non_empty LAYER_PARASITICS_FILE] } {
+  log_cmd source $::env(LAYER_PARASITICS_FILE)
+} else {
+  log_cmd source $::env(PLATFORM_DIR)/setRC.tcl
+}
 
 proc do_dpl { } {
   # Only for use with hybrid rows

flow/scripts/load.tcl

@@ -32,7 +32,11 @@ proc load_design { design_file sdc_file } {
     log_cmd source $::env(PLATFORM_DIR)/derate.tcl
   }
 
-  source $::env(PLATFORM_DIR)/setRC.tcl
+  if { [env_var_exists_and_non_empty LAYER_PARASITICS_FILE] } {
+    log_cmd source $::env(LAYER_PARASITICS_FILE)
+  } else {
+    log_cmd source $::env(PLATFORM_DIR)/setRC.tcl
+  }
 
   if { [env_var_equals LIB_MODEL CCS] } {
     puts "Using CCS delay calculation"

flow/scripts/open.tcl

@@ -34,7 +34,11 @@ proc read_timing { input_file } {
     source $::env(PLATFORM_DIR)/derate.tcl
   }
 
-  source $::env(PLATFORM_DIR)/setRC.tcl
+  if { [env_var_exists_and_non_empty LAYER_PARASITICS_FILE] } {
+    log_cmd source $::env(LAYER_PARASITICS_FILE)
+  } else {
+    log_cmd source $::env(PLATFORM_DIR)/setRC.tcl
+  }
   if { $design_stage >= 4 } {
     # CTS has run, so propagate clocks
     set_propagated_clock [all_clocks]

flow/scripts/variables.yaml

@@ -429,6 +429,10 @@ PLACE_SITE:
     - floorplan
   type: string
   tunable: 1
+LAYER_PARASITICS_FILE:
+  description: |
+    Path to per layer parasitics file. Defaults to $(PLATFORM_DIR)/setRC.tcl.
+  type: string
 TAPCELL_TCL:
   description: |
     Path to Endcap and Welltie cells file.