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malibertymaliberty
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Merge pull request #1571 from KrzysztofHerman/ihp-platform
IHP130 OpenPDK support for ORFS
2 parents b711f8f + 400b547 commit 24938f4

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‎flow/Makefile‎

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# DESIGN_CONFIG=./designs/gf180/jpeg/config.mk
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# DESIGN_CONFIG=./designs/gf180/riscv32i/config.mk
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# DESIGN_CONFIG=./designs/gf180/uart-blocks/config.mk
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#
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#DESIGN_CONFIG=./designs/ihp-sg13g2/aes/config.mk
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#DESIGN_CONFIG=./designs/ihp-sg13g2/ibex/config.mk
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#DESIGN_CONFIG=./designs/ihp-sg13g2/gcd/config.mk
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#DESIGN_CONFIG=./designs/ihp-sg13g2/spi/config.mk
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#DESIGN_CONFIG=./designs/ihp-sg13g2/riscv32i/config.mk
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# Default design
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DESIGN_CONFIG ?= ./designs/nangate45/gcd/config.mk
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‎flow/designs/ihp-sg13g2/aes/autotuner.json‎

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{
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"_SDC_FILE_PATH": "constraint.sdc",
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"_SDC_CLK_PERIOD": {
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"type": "float",
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"minmax": [
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1.0,
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3.7439
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],
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"step": 0
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},
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"CORE_UTILIZATION": {
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"type": "int",
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"minmax": [
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20,
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100
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],
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"step": 1
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},
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"CORE_ASPECT_RATIO": {
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"type": "float",
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"minmax": [
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0.5,
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2.0
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],
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"step": 0
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},
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"CORE_MARGIN": {
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"type": "int",
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"minmax": [
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2,
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2
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],
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"step": 0
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},
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"CELL_PAD_IN_SITES_GLOBAL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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5
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],
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"step": 1
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},
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"CELL_PAD_IN_SITES_DETAIL_PLACEMENT": {
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"type": "int",
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"minmax": [
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0,
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5
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],
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"step": 1
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},
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"_FR_LAYER_ADJUST": {
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"type": "float",
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"minmax": [
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0.1,
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0.7
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],
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"step": 0
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},
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"PLACE_DENSITY_LB_ADDON": {
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"type": "float",
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"minmax": [
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0.0,
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0.99
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],
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"step": 0
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},
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"_PINS_DISTANCE": {
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"type": "int",
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"minmax": [
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1,
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4
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],
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"step": 1
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},
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"CTS_CLUSTER_SIZE": {
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"type": "int",
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"minmax": [
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10,
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200
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],
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"step": 1
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},
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"CTS_CLUSTER_DIAMETER": {
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"type": "int",
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"minmax": [
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20,
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400
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],
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"step": 1
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},
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"_FR_FILE_PATH": "../../../platforms/sky130hd/fastroute.tcl",
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"_FR_GR_OVERFLOW": {
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"type": "int",
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"minmax": [
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1,
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1
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],
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"step": 0
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}
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}

‎flow/designs/ihp-sg13g2/aes/config.mk‎

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export DESIGN_NICKNAME = aes
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export DESIGN_NAME = aes_cipher_top
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export PLATFORM = ihp-sg13g2
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export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
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export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export CORE_UTILIZATION = 20
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export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY = 0.65
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export TNS_END_PERCENT = 100
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export USE_FILL = 1

‎flow/designs/ihp-sg13g2/aes/constraint.sdc‎

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current_design aes_cipher_top
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set clk_name clk
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set clk_port_name clk
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set clk_period 5.6
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set clk_io_pct 0.2
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set clk_port [get_ports $clk_port_name]
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create_clock -name $clk_name -period $clk_period $clk_port
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set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
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set_input_delay [expr $clk_period * $clk_io_pct] -clock $clk_name $non_clock_inputs
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set_output_delay [expr $clk_period * $clk_io_pct] -clock $clk_name [all_outputs]
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