Merge pull request #1639 from Pinata-Consulting/makefile-remove-standalone-vestiges

maliberty · web-flow · commit 24c4f4b96bf7 · 2023-11-25T18:46:09.000-08:00
makefile: remove standalone vestiges
diff --git a/flow/Makefile b/flow/Makefile
@@ -969,9 +969,7 @@ clean_finish:
 # ==============================================================================
 
 .PHONY: all
-all: $(SDC_FILE) $(WRAPPED_LIBS) $(DONT_USE_LIBS) $(OBJECTS_DIR)/klayout.lyt $(WRAPPED_GDSOAS) $(DONT_USE_SC_LIB)
-	mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
-	($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/run_all.tcl -metrics $(LOG_DIR)/run_all.json) 2>&1 | tee $(LOG_DIR)/run_all.log
+all: synth floorplan place cts route finish
 
 .PHONY: clean
 clean:
diff --git a/flow/scripts/cdl.tcl b/flow/scripts/cdl.tcl
@@ -1,4 +1,4 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 6_final.odb 6_final.sdc "Starting CDL"
+load_design 6_final.odb 6_final.sdc
 
 write_cdl -masters $::env(CDL_FILE) $::env(RESULTS_DIR)/6_final.cdl
diff --git a/flow/scripts/cts.tcl b/flow/scripts/cts.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "cts__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 3_place.odb 3_place.sdc "Starting CTS"
+load_design 3_place.odb 3_place.sdc
 
 # Clone clock tree inverters next to register loads
 # so cts does not try to buffer the inverted clocks.
diff --git a/flow/scripts/density_fill.tcl b/flow/scripts/density_fill.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 5_route.odb 5_route.sdc "Starting density fill"
+load_design 5_route.odb 5_route.sdc
 
 set_propagated_clock [all_clocks]
 
diff --git a/flow/scripts/detail_place.tcl b/flow/scripts/detail_place.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "detailedplace__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 3_4_place_resized.odb 2_floorplan.sdc "Starting detailed placement"
+load_design 3_4_place_resized.odb 2_floorplan.sdc
 
 source $::env(PLATFORM_DIR)/setRC.tcl
 
diff --git a/flow/scripts/detail_route.tcl b/flow/scripts/detail_route.tcl
@@ -5,7 +5,7 @@ if { [info exists ::env(USE_WXL)]} {
 } else {
   set db_file 5_2_fillcell.odb
 }
-load_design $db_file 4_cts.sdc "Starting detailed routing"
+load_design $db_file 4_cts.sdc
 set_propagated_clock [all_clocks]
 
 set_thread_count $::env(NUM_CORES)
diff --git a/flow/scripts/fillcell.tcl b/flow/scripts/fillcell.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "globalroute__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 5_1_grt.odb 4_cts.sdc "Starting fill cell"
+load_design 5_1_grt.odb 4_cts.sdc
 
 set_propagated_clock [all_clocks]
 
diff --git a/flow/scripts/final_report.tcl b/flow/scripts/final_report.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "finish__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 6_1_fill.odb 6_1_fill.sdc "Starting final report"
+load_design 6_1_fill.odb 6_1_fill.sdc
 
 set_propagated_clock [all_clocks]
 
diff --git a/flow/scripts/floorplan.tcl b/flow/scripts/floorplan.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "floorplan__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 1_synth.v 1_synth.sdc "Starting floorplan"
+load_design 1_synth.v 1_synth.sdc
 
 #Run check_setup
 puts "\n=========================================================================="
diff --git a/flow/scripts/floorplan_debug_macros.tcl b/flow/scripts/floorplan_debug_macros.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_1_floorplan.odb 1_synth.sdc "Debug floorplan"
+load_design 2_1_floorplan.odb 1_synth.sdc
 
 source $::env(SCRIPTS_DIR)/macro_place_util.tcl
 
diff --git a/flow/scripts/generate_abstract.tcl b/flow/scripts/generate_abstract.tcl
@@ -4,9 +4,7 @@ set stem [expr {[info exists ::env(ABSTRACT_SOURCE)] ? $::env(ABSTRACT_SOURCE) :
 
 set design_stage [lindex [split [file tail $stem] "_"] 0]
 
-set generating_comment "Generating abstract views"
-
-load_design $stem.odb $stem.sdc $generating_comment
+load_design $stem.odb $stem.sdc
 
 if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} {
   read_spef $::env(RESULTS_DIR)/$stem.spef
@@ -19,15 +17,11 @@ if {$design_stage >= 4} {
   set_propagated_clock [all_clocks]
 }
 
-puts $generating_comment
+puts "Generating abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef
 
 if {[info exist ::env(CDL_FILES)]} {
   cdl read_masters $::env(CDL_FILES)
   cdl out $::env(RESULTS_DIR)/$stem.cdl
 }
-
-if {![info exists standalone] || $standalone} {
-  exit
-}
diff --git a/flow/scripts/global_place.tcl b/flow/scripts/global_place.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "globalplace__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 3_2_place_iop.odb 2_floorplan.sdc "Starting global placement"
+load_design 3_2_place_iop.odb 2_floorplan.sdc
 
 set_dont_use $::env(DONT_USE_CELLS)
 
diff --git a/flow/scripts/global_place_skip_io.tcl b/flow/scripts/global_place_skip_io.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_floorplan.odb 2_floorplan.sdc "Starting global placement"
+load_design 2_floorplan.odb 2_floorplan.sdc
 
 if {[info exists ::env(FLOORPLAN_DEF)] || ([info exists ::env(HAS_IO_CONSTRAINTS)] && $::env(HAS_IO_CONSTRAINTS) != 0)} {
   puts "Has top down IO Constraints. Skip global placement without IOs"
diff --git a/flow/scripts/global_route.tcl b/flow/scripts/global_route.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "globalroute__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 4_cts.odb 4_cts.sdc "Starting global routing"
+load_design 4_cts.odb 4_cts.sdc
 
 if {[info exist env(PRE_GLOBAL_ROUTE)]} {
   source $env(PRE_GLOBAL_ROUTE)
diff --git a/flow/scripts/io_placement.tcl b/flow/scripts/io_placement.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc "Starting io placement"
+load_design 3_1_place_gp_skip_io.odb 2_floorplan.sdc
 
 if {[info exists ::env(FLOORPLAN_DEF)]} {
     puts "Skipping IO placement as DEF file was used to initialize floorplan."
diff --git a/flow/scripts/io_placement_random.tcl b/flow/scripts/io_placement_random.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_1_floorplan.odb 1_synth.sdc "Starting random IO placement"
+load_design 2_1_floorplan.odb 1_synth.sdc
 
 if {[info exists ::env(FLOORPLAN_DEF)]} {
     puts "Skipping IO placement as DEF file was used to initialize floorplan."
diff --git a/flow/scripts/load.tcl b/flow/scripts/load.tcl
@@ -1,37 +1,33 @@
-proc load_design {design_file sdc_file msg} {
-  if {![info exists standalone] || $standalone} {
-    # Read liberty files
-    source $::env(SCRIPTS_DIR)/read_liberty.tcl
-
-    # Read design files
-    set ext [file extension $design_file]
-    if {$ext == ".v"} {
-      read_lef $::env(TECH_LEF)
-      read_lef $::env(SC_LEF)
-      if {[info exist ::env(ADDITIONAL_LEFS)]} {
-        foreach lef $::env(ADDITIONAL_LEFS) {
-          read_lef $lef
-        }
+proc load_design {design_file sdc_file} {
+  # Read liberty files
+  source $::env(SCRIPTS_DIR)/read_liberty.tcl
+
+  # Read design files
+  set ext [file extension $design_file]
+  if {$ext == ".v"} {
+    read_lef $::env(TECH_LEF)
+    read_lef $::env(SC_LEF)
+    if {[info exist ::env(ADDITIONAL_LEFS)]} {
+      foreach lef $::env(ADDITIONAL_LEFS) {
+        read_lef $lef
       }
-      read_verilog $::env(RESULTS_DIR)/$design_file
-      link_design $::env(DESIGN_NAME)
-    } elseif {$ext == ".odb"} {
-      read_db $::env(RESULTS_DIR)/$design_file
-    } else {
-      error "Unrecognized input file $design_file"
     }
+    read_verilog $::env(RESULTS_DIR)/$design_file
+    link_design $::env(DESIGN_NAME)
+  } elseif {$ext == ".odb"} {
+    read_db $::env(RESULTS_DIR)/$design_file
+  } else {
+    error "Unrecognized input file $design_file"
+  }
 
-    # Read SDC file
-    read_sdc $::env(RESULTS_DIR)/$sdc_file
+  # Read SDC file
+  read_sdc $::env(RESULTS_DIR)/$sdc_file
 
-    if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
-      source $::env(PLATFORM_DIR)/derate.tcl
-    }
-
-    source $::env(PLATFORM_DIR)/setRC.tcl
-  } else {
-    puts $msg
+  if [file exists $::env(PLATFORM_DIR)/derate.tcl] {
+    source $::env(PLATFORM_DIR)/derate.tcl
   }
+
+  source $::env(PLATFORM_DIR)/setRC.tcl
 }
 
 #===========================================================================================
diff --git a/flow/scripts/macro_place.tcl b/flow/scripts/macro_place.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_3_floorplan_tdms.odb 1_synth.sdc "Starting macro placement"
+load_design 2_3_floorplan_tdms.odb 1_synth.sdc
 
 source $::env(SCRIPTS_DIR)/macro_place_util.tcl
 
diff --git a/flow/scripts/pdn.tcl b/flow/scripts/pdn.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_5_floorplan_tapcell.odb 1_synth.sdc "Starting PDN generation"
+load_design 2_5_floorplan_tapcell.odb 1_synth.sdc
 
 source $::env(PDN_TCL)
 pdngen
diff --git a/flow/scripts/resize.tcl b/flow/scripts/resize.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "placeopt__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 3_3_place_gp.odb 2_floorplan.sdc "Starting resizer"
+load_design 3_3_place_gp.odb 2_floorplan.sdc
 
 proc print_banner {header} {
   puts "\n=========================================================================="
diff --git a/flow/scripts/run_all.tcl b/flow/scripts/run_all.tcl
diff --git a/flow/scripts/sta-synth.tcl b/flow/scripts/sta-synth.tcl
@@ -1,2 +1,2 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 1_synth.v 1_synth.sdc "Loading synthesis results"
+load_design 1_synth.v 1_synth.sdc
diff --git a/flow/scripts/synth_metrics.tcl b/flow/scripts/synth_metrics.tcl
@@ -1,6 +1,6 @@
 utl::set_metrics_stage "synth__{}"
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 1_1_yosys.v 1_synth.sdc "Post synthesis"
+load_design 1_1_yosys.v 1_synth.sdc
 
 source $::env(SCRIPTS_DIR)/report_metrics.tcl
 report_metrics "Post synthesis" false false
diff --git a/flow/scripts/tapcell.tcl b/flow/scripts/tapcell.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_4_floorplan_macro.odb 1_synth.sdc "Starting tapcell"
+load_design 2_4_floorplan_macro.odb 1_synth.sdc
 
 if {[info exist ::env(TAPCELL_TCL)]} {
   source $::env(TAPCELL_TCL)
diff --git a/flow/scripts/tdms_place.tcl b/flow/scripts/tdms_place.tcl
@@ -1,5 +1,5 @@
 source $::env(SCRIPTS_DIR)/load.tcl
-load_design 2_2_floorplan_io.odb 1_synth.sdc "Starting TDMS placement"
+load_design 2_2_floorplan_io.odb 1_synth.sdc
 
 proc find_macros {} {
   set macros ""
diff --git a/flow/util/write_net_rc_script.tcl b/flow/util/write_net_rc_script.tcl
@@ -1,6 +1,6 @@
 source $::env(SCRIPTS_DIR)/load.tcl
 # Note 6_final.def has wires that prevent global routing.
-load_design 4_1_cts.odb 4_cts.sdc ""
+load_design 4_1_cts.odb 4_cts.sdc
 
 source $::env(UTILS_DIR)/write_net_rc.tcl
 

Original file line number	Diff line number	Diff line change
`@@ -5,7 +5,7 @@ if { [info exists ::env(USE_WXL)]} {`
`5`	`5`	`} else {`
`6`	`6`	`set db_file 5_2_fillcell.odb`
`7`	`7`	`}`
`8`		`-load_design $db_file 4_cts.sdc "Starting detailed routing"`
	`8`	`+load_design $db_file 4_cts.sdc`
`9`	`9`	`set_propagated_clock [all_clocks]`
`10`	`10`
`11`	`11`	`set_thread_count $::env(NUM_CORES)`