added ability to inject Tcl commands in synth canonicalize step

tclfmt fixes

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

docs/user/FlowVariables.md

@@ -221,6 +221,7 @@ configuration file.
 | <a name="SLEW_MARGIN"></a>SLEW_MARGIN| Specifies a slew margin when fixing max slew violations. This option allows you to overfix.| |
 | <a name="SYNTH_ARGS"></a>SYNTH_ARGS| Optional synthesis variables for yosys.| |
 | <a name="SYNTH_BLACKBOXES"></a>SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| |
+| <a name="SYNTH_CANONICALIZE_TCL"></a>SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| |
 | <a name="SYNTH_GUT"></a>SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| |
 | <a name="SYNTH_HDL_FRONTEND"></a>SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| |
 | <a name="SYNTH_HIERARCHICAL"></a>SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0|
@@ -256,6 +257,7 @@ configuration file.
 - [SDC_FILE](#SDC_FILE)
 - [SDC_GUT](#SDC_GUT)
 - [SYNTH_BLACKBOXES](#SYNTH_BLACKBOXES)
+- [SYNTH_CANONICALIZE_TCL](#SYNTH_CANONICALIZE_TCL)
 - [SYNTH_GUT](#SYNTH_GUT)
 - [SYNTH_HDL_FRONTEND](#SYNTH_HDL_FRONTEND)
 - [SYNTH_HIERARCHICAL](#SYNTH_HIERARCHICAL)

flow/designs/rapidus2hp/cva6/canonicalize.tcl

@@ -0,0 +1,4 @@
+# Remove rvfi_probes_o interface since it's not in the baseline and contributes
+# 4k ports and connections (many of which are buffers tied to tie cells)
+
+delete cva6/o:rvfi_probes_o*

flow/designs/rapidus2hp/cva6/config.mk

@@ -102,7 +102,7 @@ ifeq ($(SYNTH_HDL_FRONTEND),verific)
 else
   # Reduce the amount of resizing done between GPL and DPL
   export EARLY_SIZING_CAP_RATIO = 6
-  export CORE_UTILIZATION       = 50
+  export CORE_UTILIZATION       = 55
 endif
 
 export CORE_MARGIN            = 2
@@ -120,3 +120,6 @@ export SKIP_LAST_GASP ?= 1
 export SYNTH_MINIMUM_KEEP_SIZE ?= 40000
 
 #export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/io_constraints.tcl
+
+# Remove rvfi_probes_o interface
+export SYNTH_CANONICALIZE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/canonicalize.tcl

flow/scripts/synth_canonicalize.tcl

@@ -7,6 +7,11 @@ dict for {key value} [env_var_or_empty VERILOG_TOP_PARAMS] {
 }
 
 hierarchy -check -top $::env(DESIGN_NAME)
+
+if { [env_var_exists_and_non_empty SYNTH_CANONICALIZE_TCL] } {
+  log_cmd source $::env(SYNTH_CANONICALIZE_TCL)
+}
+
 # Get rid of unused modules
 opt_clean -purge
 # The hash of this file will not change if files not part of synthesis do not change

flow/scripts/variables.yaml

@@ -194,6 +194,12 @@ SYNTH_NETLIST_FILES:
     subsequent modules are silently ignored and only the first module is used.
   stages:
     - synth
+SYNTH_CANONICALIZE_TCL:
+  description: >
+    Specifies a Tcl script with commands to run as part of the synth
+    canonicalize step.
+  stages:
+    - synth
 LATCH_MAP_FILE:
   description: |
     List of latches treated as a black box by Yosys.