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ravi-varadarajanravi-varadarajan
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bp_quad
Signed-off-by: Ravi Varadarajan <[email protected]>
1 parent a2f6872 commit 2b4010b

19 files changed

+827808
-0
lines changed

‎flow/designs/nangate45/bp_quad/bsg_chip.sdc‎

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set sdc_version 2.0
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set_units -capacitance 1fF
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set_units -time 1000ps
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# Set the current design
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current_design bsg_chip
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create_clock -name "tag_clk" -period 5.2 -waveform {0.0 2.6} [get_ports p_bsg_tag_clk_i]
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create_clock -name "bp_clk" -period 1.3 -waveform {0.0 0.65} [get_ports p_clk_A_i]
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create_clock -name "io_master_clk" -period 1.3 -waveform {0.0 0.65} [get_ports p_clk_B_i]
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create_clock -name "router_clk" -period 1.3 -waveform {0.0 0.65} [get_ports p_clk_C_i]
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create_clock -name "sdi_a_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_ci_clk_i]
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create_clock -name "sdo_a_tkn_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_ci2_tkn_i]
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create_clock -name "sdi_b_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_co_clk_i]
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create_clock -name "sdo_b_tkn_clk" -period 2.6 -waveform {0.0 1.3} [get_ports p_co2_tkn_i]
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set_false_path -from [list \
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[get_clocks router_clk] \
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[get_clocks tag_clk] ] -to [get_clocks bp_clk]
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set_multicycle_path -to [list \
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[get_ports p_ci2_8_o] \
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[get_ports p_ci2_7_o] \
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[get_ports p_ci2_6_o] \
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[get_ports p_ci2_5_o] \
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[get_ports p_ci2_4_o] \
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[get_ports p_ci2_3_o] \
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[get_ports p_ci2_2_o] \
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[get_ports p_ci2_1_o] \
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[get_ports p_ci2_0_o] \
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[get_ports p_ci2_v_o] \
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[get_ports p_ci2_clk_o] \
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[get_ports p_co2_8_o] \
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[get_ports p_co2_7_o] \
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[get_ports p_co2_6_o] \
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[get_ports p_co2_5_o] \
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[get_ports p_co2_4_o] \
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[get_ports p_co2_3_o] \
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[get_ports p_co2_2_o] \
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[get_ports p_co2_1_o] \
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[get_ports p_co2_0_o] \
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[get_ports p_co2_v_o] \
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[get_ports p_co2_clk_o] ] -hold -start 0
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set_multicycle_path -to [list \
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[get_ports p_ci2_8_o] \
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[get_ports p_ci2_7_o] \
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[get_ports p_ci2_6_o] \
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[get_ports p_ci2_5_o] \
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[get_ports p_ci2_4_o] \
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[get_ports p_ci2_3_o] \
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[get_ports p_ci2_2_o] \
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[get_ports p_ci2_1_o] \
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[get_ports p_ci2_0_o] \
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[get_ports p_ci2_v_o] \
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[get_ports p_ci2_clk_o] \
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[get_ports p_co2_8_o] \
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[get_ports p_co2_7_o] \
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[get_ports p_co2_6_o] \
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[get_ports p_co2_5_o] \
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[get_ports p_co2_4_o] \
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[get_ports p_co2_3_o] \
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[get_ports p_co2_2_o] \
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[get_ports p_co2_1_o] \
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[get_ports p_co2_0_o] \
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[get_ports p_co2_v_o] \
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[get_ports p_co2_clk_o] ] -setup -end 1
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set_clock_gating_check -setup 0.0
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set_input_delay -clock [get_clocks tag_clk] -add_delay 1.456 [get_ports p_bsg_tag_data_i]
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set_input_delay -clock [get_clocks tag_clk] -add_delay 1.456 [get_ports p_bsg_tag_en_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_v_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_v_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_v_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_v_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_0_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_0_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_0_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_0_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_1_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_1_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_1_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_1_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_2_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_2_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_2_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_2_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_3_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_3_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_3_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_3_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_4_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_4_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_4_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_4_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_5_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_5_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_5_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_5_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_6_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_6_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_6_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_6_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_7_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_7_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_7_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_7_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -max 0.728 [get_ports p_ci_8_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -add_delay -min 0.052 [get_ports p_ci_8_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -max 0.728 [get_ports p_ci_8_i]
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set_input_delay -clock [get_clocks sdi_a_clk] -clock_fall -add_delay -min 0.052 [get_ports p_ci_8_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_v_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_v_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_v_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_v_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_0_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_0_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_0_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_0_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_1_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_1_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_1_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_1_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_2_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_2_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_2_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_2_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_3_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_3_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_3_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_3_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_4_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_4_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_4_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_4_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_5_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_5_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_5_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_5_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_6_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_6_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_6_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_6_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_7_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_7_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_7_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_7_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -max 0.728 [get_ports p_co_8_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -add_delay -min 0.052 [get_ports p_co_8_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -max 0.728 [get_ports p_co_8_i]
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set_input_delay -clock [get_clocks sdi_b_clk] -clock_fall -add_delay -min 0.052 [get_ports p_co_8_i]
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set_wire_load_mode "enclosed"
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set_clock_uncertainty -hold 0.15 [get_clocks tag_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks bp_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks bp_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks io_master_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks io_master_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks router_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks router_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks sdi_a_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks sdi_a_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks sdo_a_tkn_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks sdo_a_tkn_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks sdi_b_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks sdi_b_clk]
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set_clock_uncertainty -setup 0.15 [get_clocks sdo_b_tkn_clk]
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set_clock_uncertainty -hold 0.15 [get_clocks sdo_b_tkn_clk]

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