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Merge branch 'master' into secure-yosys0.58
Signed-off-by: Eder Monteiro <[email protected]>
2 parents dd81c92 + 0657918 commit 2d7ccda

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flow/designs/asap7/aes-block/rules-base.json

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"finish__timing__setup__tns": {
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"finish__timing__hold__ws": {

flow/designs/asap7/cva6/rules-base.json

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{
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"synth__design__instance__area__stdcell": {
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"compare": "<="
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"constraints__clocks__count": {

flow/designs/asap7/ethmac/rules-base.json

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"synth__design__instance__area__stdcell": {
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"constraints__clocks__count": {

flow/designs/asap7/ethmac_lvt/rules-base.json

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"synth__design__instance__area__stdcell": {
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"constraints__clocks__count": {

flow/designs/asap7/gcd-ccs/rules-base.json

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"synth__design__instance__area__stdcell": {
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"value": 43.107957,
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"constraints__clocks__count": {

flow/designs/asap7/gcd/rules-base.json

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"synth__design__instance__area__stdcell": {
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"value": 43.107957,
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"constraints__clocks__count": {

flow/designs/asap7/jpeg_lvt/rules-base.json

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"synth__design__instance__area__stdcell": {
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"constraints__clocks__count": {

flow/designs/asap7/riscv32i-mock-sram/rules-base.json

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"synth__design__instance__area__stdcell": {
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"constraints__clocks__count": {

flow/designs/asap7/riscv32i/rules-base.json

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"synth__design__instance__area__stdcell": {
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"constraints__clocks__count": {
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"globalroute__timing__setup__tns": {
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"globalroute__timing__hold__ws": {
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"finish__timing__hold__ws": {

flow/designs/asap7/swerv_wrapper/rules-base.json

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"value": -145602.0,
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"compare": ">="
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"finish__timing__hold__ws": {

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