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osamahammad21osamahammad21
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move macro lefs and libs to additionals
Signed-off-by: Osama <[email protected]>
1 parent 9a725d9 commit 2d8abce

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9 files changed

+65
-68
lines changed

9 files changed

+65
-68
lines changed

‎flow/designs/gf12/ariane/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,9 +11,9 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NAME)/ariane.sv2v.v \
1111
#export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
1212
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint_hier.sdc
1313

14-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef
14+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12lp_1rf_lg8_w64_byte.lef
1515

16-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12lp_1rf_lg8_w64_byte_sspg_sigcmax_0p72v_0p72v_125c.lib
16+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12lp_1rf_lg8_w64_byte_sspg_sigcmax_0p72v_0p72v_125c.lib
1717

1818
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2
1919

‎flow/designs/gf12/ariane133/config.mk‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ export VERILOG_FILES = $(PLATFORM_DIR)/ariane133/ariane.v
1111

1212
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/ariane133/ariane.sdc
1313

14-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
15-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib
14+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rw_256x16.lef
15+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rw_256x16_ffpg_sigcmin_0p88v_0p88v_m40c.lib
1616

1717
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12lp_1rf_lg8_w64_byte.gds2
1818

‎flow/designs/gf12/bp_dual/config.mk‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -21,25 +21,23 @@ export CACHED_NETLIST = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/yosy
2121

2222
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_dual_core_v0/bsg_chip.elab.v.sdc
2323

24-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
24+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
25+
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef \
26+
$(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
2527
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
2628
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
2729
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
2830
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
2931
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
3032

31-
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
32-
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef
33-
34-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
33+
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib \
34+
$(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
3535
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
3636
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
3737
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
3838
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
3939
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
4040

41-
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib
42-
4341
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
4442
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \
4543
$(PLATFORM_DIR)/gds/gf12_1rw_d256_w48_m2.gds2 \

‎flow/designs/gf12/bp_quad/config.mk‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -11,19 +11,19 @@ export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_qu
1111

1212
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_quad_core_v0/bp_quad_block/sdc/bsg_chip.sdc
1313

14-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
15-
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
16-
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
17-
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
18-
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
19-
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
20-
21-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
22-
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
23-
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
24-
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
25-
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
26-
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
14+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
15+
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
16+
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
17+
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
18+
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
19+
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
20+
21+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
22+
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
23+
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
24+
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
25+
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
26+
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
2727

2828

2929
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \

‎flow/designs/gf12/bp_single/config.mk‎

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -11,24 +11,23 @@ export VERILOG_FILES = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/yo
1111

1212
export SDC_FILE = $(PLATFORM_DIR)/bp/bsg_ac_black_parrot_single_core_v0/bsg_chip.elab.v.sdc
1313

14-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
14+
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
15+
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef \
16+
$(PLATFORM_DIR)/lef/gf12_1r1w_d32_w64_m1.lef \
1517
$(PLATFORM_DIR)/lef/gf12_1rw_d128_w116_m2_bit.lef \
1618
$(PLATFORM_DIR)/lef/gf12_1rw_d256_w48_m2.lef \
1719
$(PLATFORM_DIR)/lef/gf12_1rw_d512_w64_m2_byte.lef \
1820
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w124_m2_bit.lef \
1921
$(PLATFORM_DIR)/lef/gf12_1rw_d64_w62_m2_bit.lef
2022

21-
export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/IN12LP_GPIO18_13M9S30P.lef \
22-
$(PLATFORM_DIR)/lef/CDMM_13M_3Mx_2Cx_4Kx_2Hx_2Gx_LB.lef
23-
24-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
23+
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib \
24+
$(PLATFORM_DIR)/lib/gf12_1r1w_d32_w64_m1_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2525
$(PLATFORM_DIR)/lib/gf12_1rw_d128_w116_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2626
$(PLATFORM_DIR)/lib/gf12_1rw_d256_w48_m2_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2727
$(PLATFORM_DIR)/lib/gf12_1rw_d512_w64_m2_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2828
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w124_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
2929
$(PLATFORM_DIR)/lib/gf12_1rw_d64_w62_m2_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
3030

31-
export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/IN12LP_GPIO18_13M9S30P_TT_0P8_1P8_25.lib
3231

3332
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1r1w_d32_w64_m1.gds2 \
3433
$(PLATFORM_DIR)/gds/gf12_1rw_d128_w116_m2_bit.gds2 \

‎flow/designs/gf12/ca53/config.mk‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -8,27 +8,27 @@ export CACHED_NETLIST = $(PLATFORM_DIR)/$(DESIGN_NAME)/rtl/ca53_cpu.v
88
export SDC_FILE = $(PLATFORM_DIR)/$(DESIGN_NAME)/sdc/ca53_cpu.sdc
99

1010

11-
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef
12-
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib
1311
export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sc9mcpp84_12lp_base_lvt_c14.gds2
1412

15-
export WRAP_LEFS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
16-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
17-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
18-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
19-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
20-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
21-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
22-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef
23-
24-
export WRAP_LIBS = $(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
25-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
26-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
27-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
28-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
29-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
30-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
31-
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib
13+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sc9mcpp84_12lp_base_lvt_c14.lef /
14+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1.lef \
15+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1.lef \
16+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1.lef \
17+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1.lef \
18+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1.lef \
19+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1.lef \
20+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1.lef \
21+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lef/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1.lef
22+
23+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sc9mcpp84_12lp_base_lvt_c14_tt_nominal_max_0p80v_25c.lib \
24+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
25+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X50M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
26+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_128X60M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
27+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_160X118M2_FB1FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
28+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X12M2_FB1FS1SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib \
29+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/RFSPHD_A53_HS_256X32M2_FB1FS1SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
30+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_1024X39M4_FB2FS2SB0PG1_tt_nominal_0p80v_0p80v_25c.lib \
31+
$(PLATFORM_DIR)/$(DESIGN_NAME)/lib/SRAMSPHD_A53_HS_2048X42M4_FB2FS2SB0WM1PG1_tt_nominal_0p80v_0p80v_25c.lib
3232

3333

3434

‎flow/designs/gf12/coyote/config.mk‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,15 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/coyote.sv2v.v \
88
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
99
export ABC_AREA = 1
1010

11-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \
12-
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w128_all.lef \
13-
$(PLATFORM_DIR)/lef/gf12_2rf_lg6_w44_bit.lef \
14-
$(PLATFORM_DIR)/lef/gf12_2rf_lg8_w64_bit.lef
15-
16-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w80_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
17-
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w128_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
18-
$(PLATFORM_DIR)/lib/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
19-
$(PLATFORM_DIR)/lib/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
11+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w80_bit.lef \
12+
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w128_all.lef \
13+
$(PLATFORM_DIR)/lef/gf12_2rf_lg6_w44_bit.lef \
14+
$(PLATFORM_DIR)/lef/gf12_2rf_lg8_w64_bit.lef
15+
16+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w80_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
17+
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w128_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
18+
$(PLATFORM_DIR)/lib/gf12_2rf_lg6_w44_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
19+
$(PLATFORM_DIR)/lib/gf12_2rf_lg8_w64_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
2020

2121
export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg6_w80_bit.gds2 \
2222
$(PLATFORM_DIR)/gds/gf12_1rf_lg8_w128_all.gds2 \

‎flow/designs/gf12/swerv_wrapper/config.mk‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -14,13 +14,13 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \
1414
$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/macros.v
1515
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/constraint.sdc
1616

17-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \
18-
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \
19-
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w34_all.lef
17+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg11_w40_all.lef \
18+
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w22_all.lef \
19+
$(PLATFORM_DIR)/lef/gf12_1rf_lg8_w34_all.lef
2020

21-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg11_w40_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
22-
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w22_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
23-
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w34_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib
21+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg11_w40_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
22+
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w22_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
23+
$(PLATFORM_DIR)/lib/gf12_1rf_lg8_w34_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib
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export ADDITIONAL_GDS = $(PLATFORM_DIR)/gds/gf12_1rf_lg11_w40_all.gds2 \
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$(PLATFORM_DIR)/gds/gf12_1rf_lg6_w22_all.gds2 \

‎flow/designs/gf12/tinyRocket/config.mk‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,11 @@ export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/AsyncResetReg.v \
1414

1515
export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
1616

17-
export WRAP_LEFS = $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \
18-
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef
17+
export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_all.lef \
18+
$(PLATFORM_DIR)/lef/gf12_1rf_lg6_w32_byte.lef
1919

20-
export WRAP_LIBS = $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
21-
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
20+
export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_all_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
21+
$(PLATFORM_DIR)/lib/gf12_1rf_lg6_w32_byte_ffpg_sigcmin_0p88v_0p88v_m40c.lib \
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#$(PLATFORM_DIR)/lib/gf12_2rf_lg10_w32_bit_ffpg_sigcmin_0p88v_0p88v_m40c.lib
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