Merge branch 'master' into ihpsg13g2_at

Author: luarss

env.sh

@@ -21,3 +21,5 @@ if [[ "$OSTYPE" == "darwin"* ]]; then
   export PATH="$(brew --prefix bison)/bin:$(brew --prefix flex)/bin:$(brew --prefix tcl-tk)/bin:$PATH"
   export CMAKE_PREFIX_PATH="$(brew --prefix or-tools)"
 fi
+
+export FLOW_HOME=$DIR/flow

flow/.gitignore

@@ -2,4 +2,3 @@ settings.mk
 vars.sh
 vars.gdb
 vars.tcl
-copyright.txt

flow/Makefile

@@ -536,9 +536,10 @@ UNSET_VARS = for var in $(UNSET_VARIABLES_NAMES); do unset $$var; done
 SUB_MAKE = $(MAKE) $(foreach V,$(COMMAND_LINE_ARGS), $(if $($V),$V=$(shell echo "$($V)" | $(FLOW_HOME)/scripts/escape.sh),$V='')) --no-print-directory DESIGN_CONFIG=$(DESIGN_CONFIG)
 UNSET_AND_MAKE = @bash -c '$(UNSET_VARS); $(SUB_MAKE) $$@' --
 
-copyright.txt:
+$(OBJECTS_DIR)/copyright.txt:
 	@$(OPENROAD_CMD) $(SCRIPTS_DIR)/noop.tcl
-	@touch copyright.txt
+	mkdir -p $(OBJECTS_DIR)
+	@touch $(OBJECTS_DIR)/copyright.txt
 
 # Separate dependency checking and doing a step. This can
 # be useful to retest a stage without having to delete the
@@ -570,8 +571,8 @@ $(if $(5),$(5),$(RESULTS_DIR))/$(1)$(if $(4),$(4),.odb): $(2)
 	$$(UNSET_AND_MAKE) do-$(1)
 
 .PHONY: do-$(1)
-do-$(1): copyright.txt
-	@echo Running $(3).tcl
+do-$(1): $(OBJECTS_DIR)/copyright.txt
+	@echo Running $(3).tcl, stage $(1)
 	@(trap 'mv $(LOG_DIR)/$(1).tmp.log $(LOG_DIR)/$(1).log' EXIT; \
 	 $(OPENROAD_CMD) $(SCRIPTS_DIR)/noop.tcl 2>&1 >$(LOG_DIR)/$(1).tmp.log; \
 	 $(TIME_CMD) $(OPENROAD_CMD) -no_splash $(SCRIPTS_DIR)/$(3).tcl -metrics $(LOG_DIR)/$(1).json 2>&1 | \
@@ -858,49 +859,11 @@ do-finish:
 	mkdir -p $(LOG_DIR) $(REPORTS_DIR)
 	$(UNSET_AND_MAKE) do-6_1_fill do-6_1_fill.sdc do-6_final.sdc do-6_report do-gds elapsed
 
-.PHONY: skip_place
-skip_place: $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/2_floorplan.sdc
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_1_place_gp_skip_io.odb
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_2_place_iop.odb
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_3_place_gp.odb
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_4_place_resized.odb
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_5_place_dp.odb
-	cp $(RESULTS_DIR)/2_floorplan.odb $(RESULTS_DIR)/3_place.odb
-	cp $(RESULTS_DIR)/2_floorplan.sdc $(RESULTS_DIR)/3_place.sdc
-
-.PHONY: skip_resize
-skip_resize: $(RESULTS_DIR)/3_3_place_gp.odb
-	cp $(RESULTS_DIR)/3_3_place_gp.odb $(RESULTS_DIR)/3_4_place_resized.odb
-
-.PHONY: skip_cts
-skip_cts: $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/3_place.sdc
-	# mock all intermediate results
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_1_cts.odb
-	cp $(RESULTS_DIR)/3_place.sdc $(RESULTS_DIR)/4_cts.sdc
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/4_cts.odb
-
-.PHONY: skip_route
-skip_route: $(RESULTS_DIR)/4_cts.odb $(RESULTS_DIR)/4_cts.sdc
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/5_1_grt.odb
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/5_2_route.odb
-	cp $(RESULTS_DIR)/3_place.odb $(RESULTS_DIR)/6_1_fill.odb
-	touch $(RESULTS_DIR)/6_final.spef
-
-# A mock abstract is a fully or partially eviscerated macro. A mock
-# abstract can be useful when creating bug reports, previewing
-# macro placement, testing detailed routing, or other quick smoke-tests
-# at the top level.
-#
-# When creating a mock abstract, depending on what needs to be tested,
-# stages can be skipped.
-#
-# Leave out "skip_" targes as approperiate:
-#
-# make skip_place skip_cts skip_route generate_abstract
 .PHONY: generate_abstract
 generate_abstract: $(RESULTS_DIR)/6_final.gds $(RESULTS_DIR)/6_final.def  $(RESULTS_DIR)/6_final.v $(RESULTS_DIR)/6_final.sdc
 	$(UNSET_AND_MAKE) do-generate_abstract
 
+# Set ABSTRACT_SOURCE if you want to create an abstract from another stage than 6_final.
 .PHONY: do-generate_abstract
 do-generate_abstract:
 	mkdir -p $(LOG_DIR) $(REPORTS_DIR)
@@ -1023,7 +986,7 @@ nuke: clean_test clean_issues
 	rm -rf ./results ./logs ./reports ./objects
 	rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def
 	rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log
-	rm -f versions.txt copyright.txt dummy.guide
+	rm -f versions.txt $(OBJECTS_DIR)/copyright.txt dummy.guide
 
 .PHONY: vars
 vars:

flow/designs/asap7/mock-array/Element/constraints.sdc

@@ -14,11 +14,15 @@ set clk_port [get_ports $clk_port_name]
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
 set_clock_uncertainty -setup 20.0 [get_clocks $clk_name]
 set_clock_uncertainty -hold  20.0 [get_clocks $clk_name]
+# From top level run's metrics
+#set_clock_latency -source 350 [get_clocks $clk_name]
 
 create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name ${clk_name}_vir
 set_clock_uncertainty -setup 20.0 [get_clocks ${clk_name}_vir]
 set_clock_uncertainty -hold 20.0  [get_clocks ${clk_name}_vir]
 set_clock_latency 70 [get_clocks ${clk_name}_vir]
+# From top level run's metrics
+#set_clock_latency -source 380 [get_clocks ${clk_name}_vir]
 
 set_max_transition 250 [current_design]
 set_max_transition 100 -clock_path [all_clocks]

flow/designs/asap7/mock-array/constraints.sdc

@@ -13,7 +13,7 @@ set_clock_uncertainty 10 [get_clocks $clk_name]
 
 create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
 set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
-set_clock_latency     380 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
+set_clock_latency 380 [get_clocks ${clk_name}_vir] ;# Matching real clock latency
 
 set clk_port [get_ports $clk_port_name]
 set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]

flow/scripts/generate_abstract.tcl

@@ -16,7 +16,8 @@ if {$design_stage >= 6 && [file exists $::env(RESULTS_DIR)/$stem.spef]} {
 if {$design_stage >= 4} {
   set_propagated_clock [all_clocks]
 }
-
+# write_timing_model includes the source latency in the model
+set_clock_latency -source 0 [all_clocks]
 puts "Generating abstract views"
 write_timing_model $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lib
 write_abstract_lef -bloat_occupied_layers $::env(RESULTS_DIR)/$::env(DESIGN_NAME).lef

flow/scripts/report_metrics.tcl

@@ -152,6 +152,53 @@ proc report_metrics { stage when {include_erc true} {include_clock_skew true} }
       set path_delay -1
       set path_slack 0
     }
+
+    if { [llength [all_registers]] != 0} {
+    report_puts "\n=========================================================================="
+    report_puts "$when report_checks -path_delay max reg to reg"
+    report_puts "--------------------------------------------------------------------------"
+    report_checks -path_delay max -from [all_registers] -to [all_registers] -format full_clock_expanded >> $filename    
+    report_puts "\n=========================================================================="
+    report_puts "$when report_checks -path_delay min reg to reg"
+    report_puts "--------------------------------------------------------------------------"
+    report_checks -path_delay min -from [all_registers] -to [all_registers]  -format full_clock_expanded >> $filename         
+
+    set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay max -from [all_inputs] -to [all_registers]] 0]
+    if {$inp_to_reg_critical_path != ""} {
+      set target_clock_latency_max [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+    } else {
+      set target_clock_latency_max 0	
+    }
+
+
+    set inp_to_reg_critical_path [lindex [find_timing_paths -path_delay min -from [all_inputs] -to [all_registers]] 0]
+    if {$inp_to_reg_critical_path != ""} {
+      set target_clock_latency_min [sta::format_time [$inp_to_reg_critical_path target_clk_delay] 4]
+      set source_clock_latency [sta::format_time [$inp_to_reg_critical_path source_clk_latency] 4]
+    } else {
+      set target_clock_latency_min 0	
+      set source_clock_latency 0
+    }
+      
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path target clock latency max path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$target_clock_latency_max"
+
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path target clock latency min path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$target_clock_latency_min"
+
+    report_puts "\n=========================================================================="
+    report_puts "$when critical path source clock latency min path"
+    report_puts "--------------------------------------------------------------------------"
+    report_puts "$source_clock_latency"
+    } else {
+    puts "No registers in design"
+    }
+    # end if all_registers
+      
     report_puts "\n=========================================================================="
     report_puts "$when critical path delay"
     report_puts "--------------------------------------------------------------------------"