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jeffng-orjeffng-or
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Added mempool_group SV in prep for SV enablement
removed references to GF12 memories, which were already commented out Signed-off-by: Jeff Ng <[email protected]>
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‎flow/designs/nangate45/mempool_group/config.mk‎

Lines changed: 61 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,23 +5,73 @@ export PLATFORM = nangate45
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export SYNTH_HIERARCHICAL = 1
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export TEMP_DESIGN_DIR = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)
8-
export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v
8+
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_group.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/cf_math_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/variable_latency_interconnect/variable_latency_interconnect.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi_hier_interco.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_tile.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/cluster_interconnect/rtl/tcdm_interconnect/tcdm_interconnect_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_mux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_remap.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/mempool_cc.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_sram.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fall_through_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_xbar.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/address_scrambler.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tcdm_shim.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_axi_adapter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_cut.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_intf.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/riscv_instr.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/axi/src/axi_id_prepend.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/rr_arb_tree.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/fifo_v3.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/lzc.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_ipu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_pkg.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/isochronous_spill_register.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lookup.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_l0.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_refill.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/onehot_to_bin.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/fifo_v2.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/spill_register_flushable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/stream_arbiter_flushable.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/latch_scm.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_lsu.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/tech_cells_generic/src/rtl/tc_clk.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_handler.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch_addr_demux.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_regfile_ff.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_shared_muldiv.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/common_cells/src/deprecated/find_first_one.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_onehot.sv \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/snitch/src/snitch_icache/snitch_icache_lfsr.sv
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export VERILOG_INCLUDE_DIRS = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl \
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$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/rtl/register_interface/include
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sdc
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export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram45_256x32.lef \
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$(PLATFORM_DIR)/lef/fakeram45_64x64.lef \
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$(PLATFORM_DIR)/lef/fakeram45_128x32.lef \
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$(PLATFORM_DIR)/lef/fakeram45_128x256.lef
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$(PLATFORM_DIR)/lef/fakeram45_64x64.lef\
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export ADDITIONAL_LIBS = $(PLATFORM_DIR)/lib/fakeram45_256x32.lib \
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$(PLATFORM_DIR)/lib/fakeram45_128x32.lib \
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$(PLATFORM_DIR)/lib/fakeram45_64x64.lib \
20-
$(PLATFORM_DIR)/lib/fakeram45_128x256.lib
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$(PLATFORM_DIR)/lib/fakeram45_64x64.lib
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22-
export DIE_AREA = 0 0 4400 4400
23-
export CORE_AREA = 10 12 4390 4390
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export DIE_AREA = 0 0 1100 1100
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export CORE_AREA = 10 12 1090 1090
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25-
export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-1000 -exclude bottom:3400-4400
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export MACRO_PLACE_HALO = 10 10
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27-
export MACRO_PLACE_HALO = 10 10
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export SYNTH_USE_SLANG = 1

‎flow/designs/nangate45/mempool_group/mempool_group.sdc‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
set sdc_version 2.0
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set_units -time ns -resistance kOhm -capacitance fF -power mW -voltage V -current uA
3+
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set clock_cycle 3
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set uncertainty [expr $clock_cycle*0.02]
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set io_delay 0
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set maxFanout 16
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set maxTransition [expr $clock_cycle*0.01]
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set pre_cts_clock_latency_estimate 0.070
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set clock_port_mempool_tile clk_i
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create_clock -name clk_i -period $clock_cycle [get_ports $clock_port_mempool_tile]
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set_clock_uncertainty $uncertainty [all_clocks]
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set_input_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==in && is_on_clock_network==false"]
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set_output_delay -clock [get_clocks clk_i] -add_delay -max $io_delay [get_ports * -filter "direction==out && is_on_clock_network==false"]
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set_max_transition $maxTransition -clock_path [get_clocks clk_i]
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set_clock_latency $pre_cts_clock_latency_estimate [get_clocks clk_i]
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#set_propagated_clock [get_clocks clk_i]
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# Create virtual clock.
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create_clock -name "vclk_i" -period $clock_cycle
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set_clock_uncertainty $uncertainty [get_clocks vclk_i]
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set_clock_latency $pre_cts_clock_latency_estimate [get_clocks vclk_i]
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set_max_transition $maxTransition -clock_path [get_clocks vclk_i]
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set_case_analysis 0 [get_ports scan_enable_i]
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set_max_fanout $maxFanout [current_design]
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# False path some of the quasi-static signals.
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#set_false_path -from tile_id_i
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# TCDM Master
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set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_.*req_.*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter { name =~ tcdm_master_*req_*_o}]
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set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_master_*resp_*_o}]
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# TCDM Slave
44+
#set_input_delay [expr 0.65*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*req_*_o}]
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set_input_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_i}]
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set_output_delay [expr 0.85*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ tcdm_slave_*resp_*_o}]
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# Refill port
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#set_input_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_i}]
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#set_output_delay [expr 0.50*$clock_cycle] -clock vclk_i [get_ports -filter {name =~ refill_*_o}]
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# Reset
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set_input_delay [expr 0.30*$clock_cycle] -clock vclk_i rst_ni
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# Critical range
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# Depending on the synthesis tool used, this can be helpful.
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#set_critical_range 0.100 [current_design]

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